Axi5ArChannelInterface class

Basis for all possible AR channels.

Inheritance
Mixed-in types
Implementers

Constructors

Axi5ArChannelInterface({required Axi5BaseArChannelConfig config, bool useCrediting = false, bool sharedCredits = false, int numRp = 0, bool atomicMixInEnable = false, bool debugMixInEnable = false, bool idMixInEnable = false, bool userMixInEnable = false, bool mmuMixInEnable = false, bool qualMixInEnable = false, bool tagMixInEnable = false, bool chunkMixInEnable = false, bool opcodeMixInEnable = false})
Constructor.

Properties

act → Logic?
Arm Compression Technology.
no setterinherited
actV → Logic?
Arm Compression Technology valid.
no setterinherited
actWidth → int
ACT width.
final
addr → Logic
The address of the first transfer in a transaction.
no setterinherited
addrWidth → int
Width of the address bus.
final
atomicMixInEnable → bool
Enable Atomic signal mixin
final
atOp → Logic?
Atomic operation type for a transaction.
no setterinherited
atOpWidth → int
Width of the ATOP signal.
final
burst → Logic?
Burst type, indicates how address changes between each transfer in a transaction.
no setterinherited
burstWidth → int
Width of the BURST signal.
final
cache → Logic?
Indicates how a transaction is required to progress through a system.
no setterinherited
cacheWidth → int
Width of the CACHE signal.
final
chunkEn → Logic?
Chunking enabled for this transaction.
no setterinherited
chunkMixInEnable → bool
Enable Chunk signal mixin
final
chunkNum → Logic?
Indicates the chunk number being transferred.
no setterinherited
chunkNumWidth → int
Width of CHUNKNUM signal.
final
chunkStrb → Logic?
Indicates the chunks that are valid for this transfer.
no setterinherited
chunkStrbWidth → int
Width of CHUNKSTRB.
final
chunkV → Logic?
Indicates that a given data chunk is valid.
no setterinherited
crdt → Logic?
Give one credit on the given resource plane.
no setterinherited
crdtSh → Logic?
Give one shared credit.
no setterinherited
debugMixInEnable → bool
Enable Debug signal mixin
final
hashCode → int
The hash code for this object.
no setterinherited
id → Logic?
Identification tag for transaction.
no setterinherited
idMixInEnable → bool
Enable ID signal mixin
final
idUnq → Logic?
Coherency barrier.
no setterinherited
idWidth → int
Width of the ID signal.
final
inst → Logic?
Instruction versus data access.
no setterinherited
instPrivPresent → bool
Inst/priv support.
final
len → Logic?
Length, the exact number of data transfers in a transaction.
no setterinherited
lenWidth → int
Width of LEN signal.
final
lock → Logic?
Provides information about atomic characteristics of a transaction.
no setterinherited
loop → Logic?
Loopback signal.
no setterinherited
loopWidth → int
Loopback signal width.
final
main → bool
Helper to control which direction the signals should be coming from.
finalinherited
mecId → Logic?
Memory encryption ID of transaction.
no setterinherited
mecIdWidth → int
Width of MECID field.
final
mmuAtSt → Logic?
Address translated indicator.
no setterinherited
mmuFlow → Logic?
SMMU flow type.
no setterinherited
mmuMixInEnable → bool
Enable MMU signal mixin
final
mmuPasUnknown → Logic?
Physical address space unknown.
no setterinherited
mmuPm → Logic?
Protected mode indicator.
no setterinherited
mmuSecSid → Logic?
Secure stream ID.
no setterinherited
mmuSid → Logic?
Stream ID.
no setterinherited
mmuSsid → Logic?
Substream ID.
no setterinherited
mmuSsidV → Logic?
Substream ID valid.
no setterinherited
mmuValid → Logic?
MMU signal qualifier.
no setterinherited
modify ↔ String Function(String original)?
A function that can be used to modify all port names in a certain way.
getter/setter pairinherited
mpam → Logic?
Memory system resource partioning and monitoring.
no setterinherited
mpamWidth → int
Width of MPAM signal.
final
nsaId → Logic?
Non-secure access ID.
no setterinherited
nse → Logic?
Non-Secure Extension.
no setterinherited
numRp → int
Number of resource planes.
finalinherited
opcodeMixInEnable → bool
Enable Opcode signal mixin
final
pas → Logic?
Physical address space of transaction.
no setterinherited
pasWidth → int
Width of PAS field.
final
pbha → Logic?
Page based HW attributes.
no setterinherited
pending → Logic?
Transfer might occur in the following cycle.
no setterinherited
ports → Map<String, Logic>
Maps from the Interface's defined port name to an instance of a Logic.
no setterinherited
prefix → String
Prefix string for port declarations
finalinherited
priv → Logic?
Privileged versus unprivileged access.
no setterinherited
prot → Logic?
Protection attributes of a transaction.
no setterinherited
protWidth → int
Width of the prot field is fixed for Axi5.
final
qos → Logic?
Quality of service identifier for a transaction.
no setterinherited
qosWidth → int
Width of the QOS signal.
final
qualMixInEnable → bool
Enable Qualifier signal mixin
final
ready → Logic?
Transfer is ready.
no setterinherited
region → Logic?
Region indicator for a transaction.
no setterinherited
regionWidth → int
Width of the REGION signal.
final
rmeSupport → bool
Realm Management Extension support.
final
rp → Logic?
Indicator of resource plane.
no setterinherited
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
secSidWidth → int
Secure stream ID width.
final
sharedCrd → Logic?
Transfer using a shared credit.
no setterinherited
sharedCredits → bool
Include shared crediting.
finalinherited
sidWidth → int
Stream ID width.
final
size → Logic?
Size, the number of bytes in each data transfer in a transaction.
no setterinherited
sizeWidth → int
Width of the SIZE signal.
final
snoop → Logic?
Opcode for snoop requests.
no setterinherited
snpWidth → int
Width of the SNOOP signal.
final
ssidWidth → int
Substream ID width.
final
subInterfaces → Map<String, PairInterface>
A mapping from sub-interface names to instances of sub-interfaces.
no setterinherited
subSysId → Logic?
Subsystem ID.
no setterinherited
subSysIdWidth → int
Subsystem ID width.
final
supportGdi → bool
GDI support.
final
supportRmeAndPasMmu → bool
RME and PAS support.
final
tagMixInEnable → bool
Enable Tag signal mixin
final
tagOp → Logic?
Tag operation.
no setterinherited
trace → Logic?
Trace signal.
no setterinherited
tracePresent → bool
Trace present.
final
untranslatedTransVersion → int
Version of the untranslated transactions spec (1-4).
final
useCrediting → bool
Should we use crediting.
finalinherited
useFlow → bool
Flow support.
final
useIdUnq → bool
Should the IDUNQ field be present.
final
useLock → bool
Controls the presence of LOCK signal.
final
useNsaId → bool
Control for using NSAID.
final
usePbha → bool
Control for using PBHA.
final
user → Logic?
User extension.
no setterinherited
userMixInEnable → bool
Enable User signal mixin
final
userWidth → int
Width of the USER signal.
final
useTagging → bool
Support tagging feature.
final
valid → Logic
The transaction is valid.
no setterinherited

Methods

addSubInterface<PairInterfaceType extends PairInterface>(String name, PairInterfaceType subInterface, {bool reverse = false, String uniquify(String original)?}) → PairInterfaceType
Registers a new subInterface on this PairInterface, enabling a simple way to build hierarchical interface definitions.
inherited
clone() → Axi5ArChannelInterface
Copy Constructor.
override
conditionalDriveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → Conditional
Makes this conditionally drive interface signals tagged with tags on other.
inherited
conditionalReceiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → Conditional
Makes this signals tagged with tags be driven conditionally by other.
inherited
connectIO(Module module, Interface srcInterface, {Iterable<PairDirection>? inputTags, Iterable<PairDirection>? outputTags, Iterable<PairDirection>? inOutTags, String uniquify(String original)?}) → void
Calls Interface.connectIO for ports of this interface as well as hierarchically for all subInterfaces.
inherited
driveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this drive interface signals tagged with tags on other.
inherited
getPorts([Iterable<PairDirection>? tags]) → Map<String, Logic>
Returns all interface ports associated with the provided tags as a Map from the port name to the Logic port.
inherited
makeAtomicPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeChunkPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeDebugPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeIdPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeMemoryAttributePorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeMemPartTagPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeMmuPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeOpcodePorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeProtPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeQualifierPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeRequestPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeUserPorts() → void
Helper to instantiate ACE specific request ports.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
pairConnectIO(Module module, Interface<PairDirection> srcInterface, PairRole role, {String uniquify(String original)?}) → void
A simplified version of connectIO for PairInterfaces where by only specifying the role, the input and output tags can be inferred.
inherited
port(String name) → Logic
Accesses a port named name.
inherited
receiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this signals tagged with tags be driven by other.
inherited
setPorts(List<Logic> ports, [Iterable<PairDirection>? tags]) → void
Adds a collection of ports to this Interface, each associated with all of tags.
inherited
toString() → String
A string representation of this object.
inherited
tryPort(String name) → Logic?
Provides the port named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool
The equality operator.
inherited