SliceInterfacePortReference class

A reference to a sliced portion of an interface port.

This class combines the functionality of SlicePortReference with InterfacePortReference to provide access to specific bits or array elements within an interface port.

Inheritance
Mixed-in types

Constructors

SliceInterfacePortReference.new(BridgeModule module, String portName, {required InterfaceReference<PairInterface> interfaceReference, List<int>? dimensionAccess, int? sliceUpperIndex, int? sliceLowerIndex})
Creates a reference to a sliced interface port.
SliceInterfacePortReference.fromString(InterfaceReference<PairInterface> interfaceReference, String portAccessString)
Creates a slice reference from a port access string.
factory

Properties

dimensionAccess ↔ List<int>?
Array dimension and/or bit indices for multi-dimensional array access.
latefinalinherited
direction → PortDirection
The effective direction of this port based on interface role and port tags.
no setterinherited
hashCode → int
The hash code for this object.
no setterinherited
hasSlicing → bool
Whether this reference includes slicing.
no setterinherited
interfaceReference → InterfaceReference<PairInterface>
The interface that contains this port.
final
isDirectionless → bool
Whether this port has no directional tags.
no setterinherited
module → BridgeModule
The BridgeModule that this reference belongs to.
finalinherited
port → Logic
Provides a reference to a Logic on an interface in this reference.
no setterinherited
portName → String
The name of the port that this reference points to.
finalinherited
portSubset → dynamic
The port subset that this reference represents.
latefinalinherited
portSubsetLogic → Logic
A Logic representation of the port subset.
latefinalinherited
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
sliceLowerIndex ↔ int?
The lower bound of the slice (inclusive).
latefinalinherited
sliceUpperIndex ↔ int?
The upper bound of the slice (inclusive).
latefinalinherited
subsetDimensions → List<int>?
The array dimensions of the port subset, if applicable.
no setterinherited
subsetElementWidth → int
The bit width of the port subset this reference represents.
no setterinherited
width → int
The bit width of this port reference.
latefinalinherited

Methods

drivesLogic(Logic other) → void
Drives a Logic signal with this port's value.
inherited
gets(PortReference other) → void
Connects this port to be driven by other.
inherited
getsLogic(Logic other) → void
Connects this port to be driven by a Logic signal.
inherited
getUpdatedSliceIndices(int endIndex, int startIndex) → (int, int)
Computes new slice indices when creating a sub-slice of this reference.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
punchDownTo(BridgeModule subModule, {String? newPortName}) → PortReference
Creates a matching port in a submodule and connects them.
inherited
punchUpTo(BridgeModule parentModule, {String? newPortName}) → PortReference
Creates a matching port in the parent module and connects them.
inherited
replicateTo(BridgeModule newModule, PortDirection direction, {String? newPortName}) → PortReference
Creates a new port in the specified module with the given direction.
inherited
slice(int endIndex, int startIndex) → SliceInterfacePortReference
Creates a slice of this port from endIndex down to startIndex.
override
tieOff([dynamic value = 0]) → void
Ties this port to a constant value.
inherited
toString() → String
A string representation of this object.
inherited

Operators

operator ==(Object other) → bool
The equality operator.
inherited
operator [](int index) → PortReference
Gets a single bit of this port at the specified index.
inherited