None yet
conf_object, log_object, apic_bus_to_apic, apic_cpu, apic_timer, interrupt_cpu, x86_rar_interrupt, apic_inter_core_smi_handling, int_register
- cell-change
- Notifier that is triggered after the object's cell was changed.
- object-delete
- Notifier that is triggered just before Simics object is deleted.
- queue-change
- Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.
- bank.apic_regs
-
x2apic_v2.ApicBankPort
– register bank
- port.freq_listener
-
x2apic_v2.frequency_listener_port
– A port class that implements frequency_listener_interface_t
-
info
– print information about the object
-
status
– print status of the object
-
arbitration_id
-
Optional attribute;
read/write access; type:
i
Arbitration ID
-
apic_type
-
Optional attribute;
read/write access; type:
s
APIC type (P4, P6, or X2)
-
cpu
-
Required attribute;
read/write access; type:
o
Target processor implementing the X86 and PROCESSOR_INFO_V2 interfaces. The APIC will assume ownership of the APICBASE MSR if the processor implements the X86_MSR interface. If the processor does not implement the X86_MSR interface, then the APIC needs to be mapped and potentially moved by some other logic.
-
physical_broadcast_address
-
Optional attribute;
read/write access; type:
i
Current broadcast address for interprocessor interrupts and interrupts from the I/O-APIC. Default value is FFh (0Fh for Pentium® (classic) family or P6 family processors); FFFFFFFFh in x2APIC mode
-
priority
-
Optional attribute;
read/write access; type:
[[[ii]{2}]{16}]
(((state, vector){2}){16}). Interrupt slots.
-
interrupt_posted
-
Optional attribute;
read/write access; type:
b
Interrupt signal raised
-
count_in_progress
-
Optional attribute;
read/write access; type:
b
Count is in progress
-
p4_x2apic
-
Optional attribute;
read/write access; type:
b
When set to TRUE it allows write to ia32_apic_base[10] bit without GP with apic_type != X2, but value of this bit won't be changed by write operation of the WRMSR instruction.
-
cpu_bus_divisor
-
Optional attribute;
read/write access; type:
f
Divisor between CPU frequency and bus frequency used by the APIC timer. Ignored if invariant TSC is available
-
ext_int_obj
-
Optional attribute;
read/write access; type:
o|n
Object pending with delivery mode ExtINT
-
frequency
-
Optional attribute;
read/write access; type:
i
System Bus Frequency in Hz. Ignored if invariant TSC is available
-
apic_bus
-
Optional attribute;
read/write access; type:
o|n
Bus implementing the apic-bus interface.
-
apic_id
-
Pseudo attribute;
read/write access; type:
i
APIC ID as stored in APIC_ID register but 'decoded' according to current APIC mode.
-
apicbase_msr_write
-
Pseudo attribute;
write-only access; type:
[ii]
Force a value change in IA32_APICBASE_MSR with side effects. The first integer is the value, the second the access type. 0 means attribute access, 1 means instruction access.
-
post_smi_delay
-
Optional attribute;
read/write access; type:
i
How many cycles will CPU run after SMI before stalling itself till the end of time quantum
-
x2apic_mode_only
-
Optional attribute;
read/write access; type:
b
True if the APIC only supports x2APIC mode and can not be disabled.
-
interrupt_subscriber
-
Optional attribute;
read/write access; type:
o|n
Set an object that will subscribe to the interrupts that the APIC generates. The object must implement the interrupt_subscriber_interface_t interface.
x2apic-c++
register bank
conf_object, log_object, transaction, register_view, register_view_read_only, bank_instrumentation_subscribe, instrumentation_order
- bank-register-value-change
- Notifier that is triggered when bank register value changes.
- cell-change
- Notifier that is triggered after the object's cell was changed.
- object-delete
- Notifier that is triggered just before Simics object is deleted.
- queue-change
- Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.
-
wait-for-get
– issue an inquiry read transaction and wait for it to complete
-
wait-for-read
– issue a read transaction and wait for it to complete
-
wait-for-set
– issue an inquiry write transaction and wait for it to complete
-
wait-for-write
– issue a write transaction and wait for it to complete
A port class that implements frequency_listener_interface_t
conf_object, log_object, frequency_listener
- cell-change
- Notifier that is triggered after the object's cell was changed.
- object-delete
- Notifier that is triggered just before Simics object is deleted.
- queue-change
- Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.