generic_pcie_switch

Description

The generic_pcie_switch_port class implements a generic PCIe switch port.

The port is hotpluggable, handles I/O, memory and prefetchable transactions and has configurable vendor and device IDs. It does not implement any memory or I/O BARs. It exposes PCI Express 2.0 and MSI-64 capabilities.

Interfaces Implemented

conf_object, log_object, bridge, io_memory, pci_bridge, pci_device, pci_express, pci_express_hotplug, pci_upstream

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Port Objects

bank.pci_config: generic_pcie_switch_port.pci_config – The PCI configuration space.

Commands for this class

info – print information about the object
print-pci-config-regs – deprecated print PCI configuration registers
status – print status of the object

Attributes

config_registers: Pseudo attribute; read-only access; type: [i*]
The PCI configuration registers, each 32 bits in size.
expansion_rom_size: Optional attribute; read/write access; type: i
The size of the expansion ROM mapping.
is_upstream: Optional attribute; read/write access; type: b
Set to true for upstream port object
mapping_setup: Optional attribute; read/write access; type: [i{15}]
Attributes for the different bridge mappings: io-memory up/down, memory up/down, prefetchable memory down: (io_down.priority, io_down.align_size, io_down.endian, mem_down.priority, mem_down.align_size, mem_down.endian, pref_down.priority, pref_down.align_size, pref_down.endian, io_up.priority, io_up.align_size, io_up.endian, mem_up.priority, mem_up.align_size, mem_up.endian)
pci_bus: Optional attribute; read/write access; type: o|[os]|n
The PCI bus this device is connected to, implementing the pci-bus interface.
Required interfaces: io_memory, pci_bus, pci_express.
port_num: Optional attribute; read/write access; type: i
Port number
secondary_bus: Required attribute; read/write access; type: o|[os]
Secondary bus
Required interfaces: io_memory, pci_bus, pci_downstream, pci_express.

Provided By

generic-pcie-switch-port

Description

The PCI configuration space.

Interfaces Implemented

conf_object, log_object, bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Commands for interface bank_instrumentation_subscribe

bp-break-bank – set device access break
bp-run-until-bank – run until specified device access occurs
bp-trace-bank – enable tracing of device accesses
bp-wait-for-bank – wait for specified device access

Commands for interface instrumentation_order

instrumentation-move – reorder instrumentation connections
instrumentation-order – list instrumentation order for object

Attributes

bist: Optional attribute; read/write access; type: i
Build-in Self Test
bridge_control: Optional attribute; read/write access; type: i
Bridge Control
cache_line_size: Optional attribute; read/write access; type: i
CacheLine Size
capabilities_ptr: Pseudo attribute; read/write access; type: i
Capabilities Pointer
class_code: Optional attribute; read/write access; type: i
Class Code
command: Optional attribute; read/write access; type: i
Command Register
device_id: Optional attribute; read/write access; type: i
Device ID
exp_capabilities: Optional attribute; read/write access; type: i
PCI Express Capabilities Register
exp_capability_header: Optional attribute; read/write access; type: i
PCI Express Capability List Register
exp_dev_cap: Optional attribute; read/write access; type: i
Device Capabilities Register
exp_dev_cap2: Optional attribute; read/write access; type: i
Device Capabilities 2 Register
exp_dev_control: Optional attribute; read/write access; type: i
Device Control Register
exp_dev_control2: Optional attribute; read/write access; type: i
Device control 2 Register
exp_dev_status: Optional attribute; read/write access; type: i
Device Status Register
exp_dev_status2: Optional attribute; read/write access; type: i
Device status 2 Register
exp_link_cap: Optional attribute; read/write access; type: i
Link Capabilities Register
exp_link_cap2: Optional attribute; read/write access; type: i
Link Capabilities 2 Register
exp_link_control: Optional attribute; read/write access; type: i
Link Control Register
exp_link_control2: Optional attribute; read/write access; type: i
Link Control 2 Register
exp_link_status: Optional attribute; read/write access; type: i
Link Status Register
exp_link_status2: Optional attribute; read/write access; type: i
Link Status 2 Register
exp_root_control: Optional attribute; read/write access; type: i
Root Control Register
exp_root_status: Optional attribute; read/write access; type: i
Root Status
exp_slot_cap: Optional attribute; read/write access; type: i
Slot Capabilities Register
exp_slot_cap2: Optional attribute; read/write access; type: i
Slot Capabilities 2 Register
exp_slot_control: Optional attribute; read/write access; type: i
Slot Control Register
exp_slot_control2: Optional attribute; read/write access; type: i
Slot Control 2 Register
exp_slot_status: Optional attribute; read/write access; type: i
Slot Status Register
exp_slot_status2: Optional attribute; read/write access; type: i
Slot Status 2 Register
header_type: Optional attribute; read/write access; type: i
Header Type
interrupt_line: Optional attribute; read/write access; type: i
Interrupt Line
interrupt_pin: Optional attribute; read/write access; type: i
Interrupt Pin
interrupts: Optional attribute; read/write access; type: i
Raised _internal_ interrupts
io_base: Optional attribute; read/write access; type: i
I/O Base
io_base_upper: Optional attribute; read/write access; type: i
I/O Base Upper 16 Bits
io_limit: Optional attribute; read/write access; type: i
I/O Limit
io_limit_upper: Optional attribute; read/write access; type: i
I/O Limit Upper 16 Bits
irq_pin_count: Optional attribute; read/write access; type: [i{4}]
Forwarded interrupt count for bridges
latency_timer: Optional attribute; read/write access; type: i
Latency Timer
memory_base: Optional attribute; read/write access; type: i
Memory Base
memory_limit: Optional attribute; read/write access; type: i
Memory Limit
msi_address: Optional attribute; read/write access; type: i
Message Address
msi_capability_header: Optional attribute; read/write access; type: i
Capability Header
msi_control: Optional attribute; read/write access; type: i
Message Control
msi_data: Optional attribute; read/write access; type: i
Message Data
msi_upper_address: Optional attribute; read/write access; type: i
Message Upper Address
prefetchable_base: Optional attribute; read/write access; type: i
Prefetchable Memory Base
prefetchable_base_upper: Optional attribute; read/write access; type: i
Prefetchable Memory Base Upper 32 Bits
prefetchable_limit: Optional attribute; read/write access; type: i
Prefetchable Memory Limit
prefetchable_limit_upper: Optional attribute; read/write access; type: i
Prefetchable Memory Limit Upper 32 Bits
primary_bus_number: Optional attribute; read/write access; type: i
Primary Bus Number
revision_id: Optional attribute; read/write access; type: i
Revision ID
secondary_bus_number: Optional attribute; read/write access; type: i
Secondary Bus Number
secondary_latency_timer: Optional attribute; read/write access; type: i
Secondary Latency Timer
secondary_status: Optional attribute; read/write access; type: i
Secondary Status
status: Optional attribute; read/write access; type: i
Status Register
subordinate_bus_number: Optional attribute; read/write access; type: i
Subordinate Bus Number
vendor_id: Optional attribute; read/write access; type: i
Vendor ID