riscv_clint

Description

RISC-V Core-Level Interrupt Block

Interfaces Implemented

conf_object, log_object, riscv_coprocessor

Port Objects

bank.regs (bank_instrumentation_subscribe, instrumentation_order, register_view, register_view_read_only, transaction)
port.CLOCK_DISABLE (signal)
port.HRESET (signal)
port.POWER (signal)

Notifiers

state-change

Provided By

riscv-interrupt-controllers

Attributes

freq_mhz

Required attribute; read/write access; type: float. Frequency in Mega-Hertz of mtime

hart

Pseudo attribute; read/write access; type: [o*]. HARTs or CLICs connected to this CLINT

msip

Optional attribute; read/write access; type: [o|[os]|n{0:64}]. The MSIP signal targets

Required interfaces: signal.

mtime_read_cycles

Optional attribute; read/write access; type: integer. Number of cycles to stall when reading mtime

mtip

Optional attribute; read/write access; type: [o|[os]|n{0:64}]. The MTIP signal targets

Required interfaces: signal.