To be used by devices bridging PCIe to/from e.g. host memory. Inherits
pcie_translator. Defines a port object downstream_port and a connect
host_memory to which upstream Mem transactions are forwarded, by
default. Defines a port message, to which Msg transactions are
forwarded, by default. The message port inherits the message_port
template. Other transaction types are terminated, by default.
Inherits pcie_device and pcie_translator. Defines a connect
upstream_target and a port object downstream_port. Defines a port
upstream_message_router which routes upstream messages either to itself or
forwards them further upstream or reroutes them downstream. Defines a port
upstream_message which handles upstream transactions of type Msg
directed at this PCIe port.
To be used by Downstream Switch Ports. Inherits pcie_port and
pcie_hotplug_port.
To be used by Root Ports. Inherits pcie_downstream_port.
To be used by Upstream Switch Ports. Inherits pcie_port.
Implements transaction interface where it receives and dispatches
transactions of type Msg to instances (on the same level) of the
handling_messages template. Unhandled messages will be terminated
with error or silently dropped depending on type of Msg.
Implements transaction_translator interface where it receives translator
requests of type Msg from downstream. Forwards messages depending
on pcie_msg_route atom. Messages to be routed upstream are forwarded to
parameter default_target, messages to be routed downstream are forwarded to
downstream_port and messages targeting this PCIe port are forwarded to
parameter local_target for local handling of the message.
Should be implemented by (DML) objects that wants to handle PCIe messages
dispatched by the message_port template. When a message is received on a
message_port instance, it will iterate over instances of this template (in
an undefined order) and call the message method. Note that downstream
messages have stub-methods in the pcie_config.message group and are not
handled by instancing this template.
Called by the message_port template when a PCIe message is received.
Must return PCIE_Error_Not_Set if the message is not
handled. Returning anything else means that the message was handled by
this method call.
Stub methods for an RC receiving and sending PRS messages. Inherits
handling_messages
Sends a Page Response message to addr via mt. The caller is responsible for setting the Device ID, Response Code and PRGI fields of addr (which corresponds to DW3 and DW4 in the TLP header).
Stub method, called when a Page Request message is received. Should
return true if the message was handled correctly or false if the
message could not be handled. The default implementation logs an
unimpl message and returns false.
Default PCIe translator, implementing transaction_translator. Redirects
transactions based on the pcie_type atom. Transactions are forwarded
according to parameters msg, mem, io and cfg in the group
txl_target. By default, all parameters point to the parameter def which
defaults to NULL, i.e. transactions are terminated.
Stub template for handling ATS transactions. Inherits pcie_translator.
Defines the ports ats_untranslated, ats_translated and ats_request to
which Memory transactions are forwarded according to the pcie_at
atom. All other transactions are handled according to the default behavior of
pcie_translator. The port ats_request implements transaction with the
method issue which by default logs an unimpl message and returns
PCIE_Error_Completer_Abort. The two other ports implement
transaction_translator and forward all transactions to
host_memory.map_target, by default.
Sends an ATS invalidation message via mt to an endpoint to invalidate a translated address. The caller is responsible for setting the fields of 'translated_addr'.
Inherits physical_config_bank and adds Type 1 specific registers. Automatically handles mapping of the downstream_target, according to the secondary/subordinate and base/limit registers. Handles broadcasting of downstream messages to downstream_target.
Implements the common functionality of Type 1 base address groups such as
io, memory and prefetchable. Handles mapping of the relevant
downstream ranges into the upstream target address spaces. Inherits
abstract_base_address.
Can be applied to a connect to automatically create a pcie-downstream-port
object with map targets for cfg, msg, mem and io. The interface
pcie_port_control and transaction are connected to the downstream port
of the automatically created object.
This template should only be applied to a Downstream Port of PCI Express Switch or a Root Port of PCI Express Root Complex.
When instantiating this template, an implementation of the
pcie_hotplug_events interface will be added to the device. When a method of
this interface is invoked, it will check if the device has a PCI Express
Capability Structure that has support for the incoming Hot-Plug event. If it
does, it will trigger a Hot-Plug event.
This template also adds handling of the Hot-Plug PCIe message types defined in this library.
Can be applied to objects that inherit the pcie_downstream_port or the pcie_root_port template. Applying this template will implement the pcie_link_training interface. Implementing this interface will allow the object to initiate link training by the trigger method being invoked.
The template will also set the link_training_target in the link group of the PCI Express Capability Structure in the device.
Parameters:
pcie_link_training_target: A map_target_t pointer that is not NULL
during post_init, default downstream_port.phy.map_target