III Modeling Common Hardware Components 18 Modeling Direct Memory Access (DMA)
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17 Modeling Interrupt Controllers

An interrupt controller is the link between devices generating interrupt signals and the processor. A common device typically has one or more outbound interrupt signals. The signals are connected to the interrupt controller which has an outbound interrupt signal to the processor. The interrupt controller is programmed by the processor to clear, enable, and disable interrupts.

The interrupt controller often have one or more mask, interrupt, and update registers. They may be named differently, but it is the most common set of registers. The processor use these registers to control which interrupts that are forwarded to the processor.

Interrupt signals in Simics are modeled using the signal interface. The interface has a signal_raise and a signal_lower function. A device raise an interrupt using the signal_raise and lowers the interrupt using the signal_lower function.

17.1 Edge Triggered and Level Triggered

Interrupts are either level triggered or edge triggered. Assume that an interrupt controller has an outbound signal port connected to the processor and that the signal is called out. A device that can generate interrupts has an outbound interrupt port connected to the interrupt controller; this interrupt signal is called in. The signals can either be high or low. The interrupt controller typically has a couple of control registers, controlling which interrupts are masked and which are not. A masked interrupt signal is not forwarded to the processor.

Assume that the device raises the in signal from low to high, and that the signal is not masked by the interrupt controller. The interrupt controller will then raise the out signal from low to high, regardless of whether the signal is level or edge triggered. The difference between level and edge triggering is only visible if the in signal is raised while the interrupt is masked, i.e., disabled. In this case, the out signal will not be changed, but when the interrupt is unmasked later, i.e., the interrupt is enabled by the processor, the out signal will go from low to high only if it is level triggered. An edge triggered signal will only affect the signal on signal flanks.

The out signal is lowered when the device lowers the in signal from high to low. The out signal can also be lowered by the processor by clearing the interrupt if the signal is edge triggered. A signal which is level triggered is not lowered when the interrupt is cleared in the interrupt controller. In some cases the signal will go from high to low to high when clearing a level triggered signal.

III Modeling Common Hardware Components 18 Modeling Direct Memory Access (DMA)