LtiLrChannelInterface class

Basis for all possible LR channels.

Inheritance
Mixed-in types

Constructors

LtiLrChannelInterface({required LtiLrChannelConfig config, int vcCount = 1, bool debugMixInEnable = false, bool idMixInEnable = false, bool userMixInEnable = false})
Constructor.

Properties

addr → Logic
Address.
no setter
addrWidth → int
Address width.
final
attr → Logic
Attr.
no setter
busy → Logic?
Busy indicator.
no setterinherited
credit → Logic?
Credit return.
no setterinherited
ctag → Logic
CTAG.
no setter
ctagWidth → int
CTAG width.
final
debugMixInEnable → bool
Enable Debug signal mixin
final
hashCode → int
The hash code for this object.
no setterinherited
hwAttr → Logic
HW Attr.
no setter
id → Logic?
Identification tag for transaction.
no setterinherited
idMixInEnable → bool
Enable ID signal mixin
final
idUnq → Logic?
Coherency barrier.
no setterinherited
idWidth → int
Width of the ID signal.
final
inst → Logic?
Instruction versus data access.
no setterinherited
instPrivPresent → bool
Inst/priv support.
final
loop → Logic?
Loopback signal.
no setterinherited
loopWidth → int
Loopback signal width.
final
main → bool
Helper to control which direction the signals should be coming from.
finalinherited
mecId → Logic?
MECID.
no setter
mecIdWidth → int
MECID WIDTH.
final
modify ↔ String Function(String original)?
A function that can be used to modify all port names in a certain way.
getter/setter pairinherited
mpam → Logic?
MPAM.
no setter
mpamWidth → int
MPAM width.
final
nse → Logic?
Non-Secure Extension.
no setterinherited
pas → Logic?
Physical address space of transaction.
no setterinherited
pasWidth → int
Width of PAS field.
final
ports → Map<String, Logic>
Maps from the Interface's defined port name to an instance of a Logic.
no setterinherited
prefix → String
Prefix string for port declarations
finalinherited
priv → Logic?
Privileged versus unprivileged access.
no setterinherited
prot → Logic?
Protection attributes of a transaction.
no setterinherited
protWidth → int
Width of the prot field is fixed for Axi5.
final
resp → Logic?
Read response, indicates the status of a read transfer.
no setterinherited
respWidth → int
Width of the RESP signal.
final
rmeSupport → bool
Realm Management Extension support.
final
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
size → Logic
SIZE.
no setter
subInterfaces → Map<String, PairInterface>
A mapping from sub-interface names to instances of sub-interfaces.
no setterinherited
trace → Logic?
Trace signal.
no setterinherited
tracePresent → bool
Trace present.
final
useBusy → bool
Include the BUSY signal.
final
useIdUnq → bool
Should the IDUNQ field be present.
final
user → Logic?
User extension.
no setterinherited
userMixInEnable → bool
Enable User signal mixin
final
userWidth → int
Width of the USER signal.
final
valid → Logic
The transaction is valid.
no setterinherited
vc → Logic?
Virtual channel identifier.
no setterinherited
vcCount → int
Number of virtual channels.
finalinherited

Methods

addSubInterface<PairInterfaceType extends PairInterface>(String name, PairInterfaceType subInterface, {bool reverse = false, String uniquify(String original)?}) → PairInterfaceType
Registers a new subInterface on this PairInterface, enabling a simple way to build hierarchical interface definitions.
inherited
clone() → LtiLrChannelInterface
Copy Constructor.
override
conditionalDriveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → Conditional
Makes this conditionally drive interface signals tagged with tags on other.
inherited
conditionalReceiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → Conditional
Makes this signals tagged with tags be driven conditionally by other.
inherited
connectIO(Module module, Interface srcInterface, {Iterable<PairDirection>? inputTags, Iterable<PairDirection>? outputTags, Iterable<PairDirection>? inOutTags, String uniquify(String original)?}) → void
Calls Interface.connectIO for ports of this interface as well as hierarchically for all subInterfaces.
inherited
driveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this drive interface signals tagged with tags on other.
inherited
getPorts([Iterable<PairDirection>? tags]) → Map<String, Logic>
Returns all interface ports associated with the provided tags as a Map from the port name to the Logic port.
inherited
makeDebugPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeIdPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeProtPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeResponsePorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeUserPorts() → void
Helper to instantiate ACE specific request ports.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
pairConnectIO(Module module, Interface<PairDirection> srcInterface, PairRole role, {String uniquify(String original)?}) → void
A simplified version of connectIO for PairInterfaces where by only specifying the role, the input and output tags can be inferred.
inherited
port(String name) → Logic
Accesses a port named name.
inherited
receiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this signals tagged with tags be driven by other.
inherited
setPorts(List<Logic> ports, [Iterable<PairDirection>? tags]) → void
Adds a collection of ports to this Interface, each associated with all of tags.
inherited
toString() → String
A string representation of this object.
inherited
tryPort(String name) → Logic?
Provides the port named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool
The equality operator.
inherited