Csr class

Logic representation of a CSR.

Semantically, a register can be created with no fields. In this case, a single implicit field is created that is read/write and the entire width of the register.

Inheritance
Available extensions

Constructors

Csr(CsrInstanceConfig config)
Factory constructor for Csr.
factory

Properties

access → CsrAccess
Getter for the access control of the CSR.
no setter
addr → int
Getter for the address of the CSR.
no setter
arrayIndex → int?
If this is a part of a LogicArray, the index within that array. Othwerise, returns null.
no setterinherited
bit → LogicValue
The current active value of this signal if it has width 1, as a LogicValue.
no setterinherited
changed → Stream<LogicValueChanged>
A Stream of LogicValueChanged events which triggers at most once per Simulator tick, iff the value of the Logic has changed.
latefinalinherited
config → CsrInstanceConfig
Configuration for the CSR.
no setter
dstConnections → Iterable<Logic>
An Iterable of all Logics that are being directly driven by this.
no setterinherited
elements → List<Logic>
All elements of this structure.
latefinalinherited
fields → List<CsrFieldConfig>
Getter for the field configuration of the CSR
no setter
glitch → SynchronousEmitter<LogicValueChanged>
A stream of LogicValueChanged events for every time the signal transitions at any time during a Simulator tick.
latefinalinherited
hashCode → int
The hash code for this object.
no setterinherited
isArrayMember → bool
True if this is a member of a LogicArray.
no setterinherited
isBackdoorReadable → bool
Accessor to the architectural backdoor readability of the register.
no setter
isBackdoorWritable → bool
Accessor to the architectural backdoor writability of the register.
no setter
isFrontdoorReadable → bool
Accessor to the architectural frontdoor readability of the register.
no setter
isFrontdoorWritable → bool
Accessor to the architectural frontdoor writability of the register.
no setter
isInOut → bool
Returns true iff this signal is an inOut of its parent Module.
latefinalinherited
isInput → bool
Returns true iff this signal is an input of its parent Module.
latefinalinherited
isNet → bool
Indicates whether this signal behaves like a LogicNet, allowing multiple drivers.
no setterinherited
isOutput → bool
Returns true iff this signal is an output of its parent Module.
latefinalinherited
isPort → bool
Returns true iff this signal is an input, output, or inOut of its parent Module.
latefinalinherited
leafElements → List<Logic>
A list of all leaf-level elements at the deepest hierarchy of this structure provided in index order.
latefinalinherited
name → String
The name of this signal.
finalinherited
naming → Naming
Controls the naming (and renaming) preferences of this signal in generated outputs.
no setterinherited
negedge → Stream<LogicValueChanged>
A Stream of LogicValueChanged events which triggers at most once per Simulator tick, iff the value of the Logic has changed from 1 to 0.
no setterinherited
nextChanged → Future<LogicValueChanged>
Triggers at most once, the next time that this Logic changes value at the end of a Simulator tick.
no setterinherited
nextNegedge → Future<LogicValueChanged>
Triggers at most once, the next time that this Logic changes value at the end of a Simulator tick from 1 to 0.
no setterinherited
nextPosedge → Future<LogicValueChanged>
Triggers at most once, the next time that this Logic changes value at the end of a Simulator tick from 0 to 1.
no setterinherited
packed → Logic
Packs all elements into one flattened bus.
latefinalinherited
parentModule ↔ Module?
The Module that this Logic exists within.
getter/setter pairinherited
parentStructure → LogicStructure?
If this is a part of a LogicStructure, the structure which this is a part of. Otherwise, null.
no setterinherited
posedge → Stream<LogicValueChanged>
A Stream of LogicValueChanged events which triggers at most once per Simulator tick, iff the value of the Logic has changed from 0 to 1.
no setterinherited
previousValue → LogicValue?
The value of this signal before the most recent Simulator.tick had completed. It will be null before the first tick after this signal is created.
no setterinherited
resetValue → int
Getter for the reset value of the CSR.
no setter
reversed → Logic
Returns a version of this Logic with the bit order reversed.
latefinalinherited
rsvdIndices → List<int>
A list of indices of all of the reserved fields in the CSR. This is necessary because the configuration does not explicitly define reserved fields, but they must be accounted for in certain logic involving the CSR.
final
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
srcConnection → Logic?
A LogicStructure never has a direct source driving it, only its elements do, so always returns null.
no setterinherited
srcConnections → Iterable<Logic>
All Logics driving this, if any.
no setterinherited
structureName → String
Returns the name relative to the parentStructure-defined hierarchy, if one exists. Otherwise, this is the same as name.
no setterinherited
value → LogicValue
The current active value of this signal.
no setterinherited
valueBigInt → BigInt
The current valid active value of this signal as a BigInt.
no setterinherited
valueInt → int
The current valid active value of this signal as an int.
no setterinherited
width → int
The number of bits in this signal.
latefinalinherited

Methods

abs() → Logic
Calculates the absolute value of a signal, assuming that the number is a two's complement.
inherited
and() → Logic
Unary AND.
inherited
assignSubset(List<Logic> updatedSubset, {int start = 0}) → void
Performs an assignment operation on a portion this signal to be driven by updatedSubset. Each index of updatedSubset will be assigned to drive the corresponding index, plus start, of this signal.
inherited
clone({String? name}) → LogicStructure
Creates a new LogicStructure with the same structure as this and cloned elements, optionally with the provided name.
inherited
decr({Logic s(Logic p1)?, dynamic val = 1}) → Conditional
Decrements each element of elements using Logic.decr.
inherited
divAssign(dynamic val, {Logic s(Logic p1)?}) → Conditional
Divide-assigns each element of elements using Logic.divAssign.
inherited
eq(dynamic other) → Logic
Logical equality.
inherited
getField(String name) → Logic
Accessor to the bits of a particular field within the CSR by name name.
getFieldConfigByName(String name) → CsrFieldConfig
Accessor to the config of a particular field within the CSR by name name.
getRange(int startIndex, [int? endIndex]) → Logic
Returns a subset Logic. It is inclusive of startIndex, exclusive of endIndex.
inherited
gets(Logic other) → void
Connects this Logic directly to be driven by other.
inherited
getWriteData(Logic wd) → Logic
Given some arbitrary data wd to write to this CSR, return the data that should actually be written based on the access control of the CSR and its fields.
gt(dynamic other) → Logic
Greater-than.
inherited
gte(dynamic other) → Logic
Greater-than-or-equal-to.
inherited
hasValidValue() → bool
Returns true iff the value of this signal is valid (no x or z).
inherited
incr({Logic s(Logic p1)?, dynamic val = 1}) → Conditional
Increments each element of elements using Logic.incr.
inherited
inject(dynamic val, {bool fill = false}) → void
Injects a value onto this signal in the current Simulator tick.
inherited
isFloating() → bool
Returns true iff all bits of the current value are floating (z).
inherited
isIn(List list) → Logic
Returns 1 (of width=1) if the Logic calling this function is in list. Else 0 (of width=1) if not present.
inherited
lt(dynamic other) → Logic
Less-than.
inherited
lte(dynamic other) → Logic
Less-than-or-equal-to.
inherited
makeUnassignable({String? reason}) → void
Makes it so that this signal cannot be assigned by any full (<=) or conditional (<) assignment.
inherited
mulAssign(dynamic val, {Logic s(Logic p1)?}) → Conditional
Multiply-assigns each element of elements using Logic.mulAssign.
inherited
named(String name, {Naming? naming}) → LogicStructure
Makes a clone, optionally with the specified name, then assigns it to be driven by this.
inherited
neq(dynamic other) → Logic
Logical inequality.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
or() → Logic
Unary OR.
inherited
pow(dynamic exponent) → Logic
Power operation
inherited
put(dynamic val, {bool fill = false}) → void
Puts a value val onto this signal, which may or may not be picked up for changed in this Simulator tick.
inherited
replicate(int multiplier) → Logic
Returns a replicated signal using ReplicationOp with new width = this.width * multiplier
inherited
rotateLeft(dynamic rotateAmount, {int? maxAmount}) → Logic

Available on Logic, provided by the RotateLogic extension

Returns a Logic rotated left by rotateAmount.
rotateRight(dynamic rotateAmount, {int? maxAmount}) → Logic

Available on Logic, provided by the RotateLogic extension

Returns a Logic rotated right by rotateAmount.
selectFrom(List<Logic> busList, {Logic? defaultValue}) → Logic
Performs a Logic index based selection on an List of Logic named busList.
inherited
setAllParentModule(Module? newParentModule) → void
Performs a recursive call of setting parentModule on all of elements and their elements for any sub-LogicStructures.
inherited
signExtend(int newWidth) → Logic
Returns a new Logic width width newWidth where new bits added are sign bits as the most significant bits. The sign is determined using two's complement, so it takes the most significant bit of the original signal and extends with that.
inherited
slice(int endIndex, int startIndex) → Logic
Accesses a subset of this signal from startIndex to endIndex, both inclusive.
inherited
toString() → String
A string representation of this object.
inherited
waitCycles(int numCycles, {Edge edge = Edge.pos}) → Future<void>

Available on Logic, provided by the LogicWaiter extension

Returns a Future which completes after the specified numCycles, where each cycle is defined as the next occurence of the specified edge.
withSet(int startIndex, Logic update) → Logic
Returns a copy of this Logic with the bits starting from startIndex up until startIndex + update.width set to update instead of their original value.
inherited
xor() → Logic
Unary XOR.
inherited
zeroExtend(int newWidth) → Logic
Returns a new Logic with width newWidth where new bits added are zeros as the most significant bits.
inherited

Operators

operator %(dynamic other) → Logic
Modulo operation.
inherited
operator &(Logic other) → Logic
Logical bitwise AND.
inherited
operator *(dynamic other) → Logic
Multiplication.
inherited
operator +(dynamic other) → Logic
Addition.
inherited
operator -(dynamic other) → Logic
Subtraction.
inherited
operator /(dynamic other) → Logic
Division.
inherited
operator <(dynamic other) → Conditional
Conditional assignment operator.
inherited
operator <<(dynamic other) → Logic
Logical left-shift.
inherited
operator <=(Logic other) → void
Connects this Logic directly to another Logic.
inherited
operator ==(Object other) → bool
The equality operator.
inherited
operator >(dynamic other) → Logic
Greater-than.
inherited
operator >=(dynamic other) → Logic
Greater-than-or-equal-to.
inherited
operator >>(dynamic other) → Logic
Arithmetic right-shift.
inherited
operator >>>(dynamic other) → Logic
Logical right-shift.
inherited
operator [](dynamic index) → Logic
Accesses the indexth bit of this signal.
inherited
operator ^(Logic other) → Logic
Logical bitwise XOR.
inherited
operator |(Logic other) → Logic
Logical bitwise OR.
inherited
operator ~() → Logic
Logical bitwise NOT.
inherited