ClockGateControlInterface constructor

ClockGateControlInterface({
  1. bool isPresent = true,
  2. bool hasEnableOverride = false,
  3. List<Logic>? additionalPorts,
  4. Logic gatedClockGenerator(
    1. ClockGateControlInterface intf,
    2. Logic clk,
    3. Logic enable
    ) = defaultGenerateGatedClock,
})

Constructs a ClockGateControlInterface with the provided arguments.

If isPresent is false, then no clock gating will occur and no clock gating logic will be generated.

If hasEnableOverride is true, then an additional enableOverride port will be generated.

additionalPorts can optionally be added to this interface, which can be useful in conjunction with a custom gatedClockGenerator. As the interface is punched through hierarchies, any modules using this interface will automatically include the additionalPorts and use the custom gatedClockGenerator for clock gating logic.

Implementation

ClockGateControlInterface({
  this.isPresent = true,
  this.hasEnableOverride = false,
  this.additionalPorts,
  this.gatedClockGenerator = defaultGenerateGatedClock,
}) : super(portsFromProvider: [
        if (hasEnableOverride) Logic.port('en_override'),
        ...?additionalPorts,
      ]);