Axi5StreamInterface class

A standard AXI5 stream interface.

Inheritance
Implementers

Constructors

Axi5StreamInterface({int idWidth = 4, int dataWidth = 64, int userWidth = 0, int destWidth = 0, bool useKeep = false, bool useLast = false, bool useWakeup = false, bool useStrb = false})
Construct a new instance of an AXI5-S interface.

Properties

crdt Logic?
Give one credit on the given resource plane.
no setterinherited
crdtSh Logic?
Give one shared credit.
no setterinherited
data Logic?
Stream data.
no setter
dataWidth int
Width of the stream data bus.
final
dest Logic?
Destination hint for the stream channel (user-defined).
no setter
destWidth int
Width of the TDEST sideband field.
final
hashCode int
The hash code for this object.
no setterinherited
id Logic?
Identifier for the stream transfer.
no setter
idWidth int
Width of the ID signal.
final
keep Logic?
Keeps, which byte lanes of data shouldn't be ignored at the destination.
no setter
last Logic?
Indicates whether this is the last data transfer in a stream.
no setter
main bool
Helper to control which direction the signals should be coming from.
finalinherited
modify String Function(String original)?
A function that can be used to modify all port names in a certain way.
getter/setter pairinherited
numRp int
Number of resource planes.
finalinherited
pending Logic?
Transfer might occur in the following cycle.
no setterinherited
ports Map<String, Logic>
Maps from the Interface's defined port name to an instance of a Logic.
no setterinherited
prefix String
Prefix string for port declarations
finalinherited
ready Logic?
Transfer is ready.
no setterinherited
rp Logic?
Indicator of resource plane.
no setterinherited
runtimeType Type
A representation of the runtime type of the object.
no setterinherited
sharedCrd Logic?
Transfer using a shared credit.
no setterinherited
sharedCredits bool
Include shared crediting.
finalinherited
strb Logic?
Data strobes, indicate which byte lanes hold valid data.
no setter
strbWidth int
Width of the strobe/keep signals.
final
subInterfaces Map<String, PairInterface>
A mapping from sub-interface names to instances of sub-interfaces.
no setterinherited
useCrediting bool
Should we use crediting.
finalinherited
useKeep bool
Presence of KEEP signal.
final
useLast bool
Presence of LAST signal.
final
user Logic?
User extension.
no setter
userWidth int
Width of the USER signal.
final
useStrb bool
Presence of STRB signal.
final
useWakeup bool
Presence of WAKEUP signal.
final
valid Logic
The transaction is valid.
no setterinherited
wakeup Logic?
Wake up.
no setter

Methods

addSubInterface<PairInterfaceType extends PairInterface>(String name, PairInterfaceType subInterface, {bool reverse = false, String uniquify(String original)?}) → PairInterfaceType
Registers a new subInterface on this PairInterface, enabling a simple way to build hierarchical interface definitions.
inherited
clone() Axi5StreamInterface
Constructs a new Axi5StreamInterface with identical parameters.
override
conditionalDriveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) Conditional
Makes this conditionally drive interface signals tagged with tags on other.
inherited
conditionalReceiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) Conditional
Makes this signals tagged with tags be driven conditionally by other.
inherited
connectIO(Module module, Interface srcInterface, {Iterable<PairDirection>? inputTags, Iterable<PairDirection>? outputTags, Iterable<PairDirection>? inOutTags, String uniquify(String original)?}) → void
Calls Interface.connectIO for ports of this interface as well as hierarchically for all subInterfaces.
inherited
driveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this drive interface signals tagged with tags on other.
inherited
getPorts([Iterable<PairDirection>? tags]) Map<String, Logic>
Returns all interface ports associated with the provided tags as a Map from the port name to the Logic port.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
pairConnectIO(Module module, Interface<PairDirection> srcInterface, PairRole role, {String uniquify(String original)?}) → void
A simplified version of connectIO for PairInterfaces where by only specifying the role, the input and output tags can be inferred.
inherited
port(String name) Logic
Accesses a port named name.
inherited
receiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this signals tagged with tags be driven by other.
inherited
setPorts(List<Logic> ports, [Iterable<PairDirection>? tags]) → void
Adds a collection of ports to this Interface, each associated with all of tags.
inherited
toString() String
A string representation of this object.
inherited
tryPort(String name) Logic?
Provides the port named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) bool
The equality operator.
inherited