Axi5LiteRChannelInterface class

AXI-5 Lite R channel.

Inheritance

Constructors

Axi5LiteRChannelInterface({required Axi5BaseRChannelConfig config, bool userMixInEnable = false, bool debugMixInEnable = false, bool responseMixInEnable = false, bool idMixInEnable = false})
Constructor.

Properties

busy → Logic?
Busy indicator.
no setterinherited
chunkEn → Logic?
Chunking enabled for this transaction.
no setterinherited
chunkMixInEnable → bool
Enable Chunk signal mixin
finalinherited
chunkNum → Logic?
Indicates the chunk number being transferred.
no setterinherited
chunkNumWidth → int
Width of CHUNKNUM signal.
finalinherited
chunkStrb → Logic?
Indicates the chunks that are valid for this transfer.
no setterinherited
chunkStrbWidth → int
Width of CHUNKSTRB.
finalinherited
chunkV → Logic?
Indicates that a given data chunk is valid.
no setterinherited
comp → Logic?
Completion response.
no setterinherited
crdt → Logic?
Give one credit on the given resource plane.
no setterinherited
crdtSh → Logic?
Give one shared credit.
no setterinherited
data → Logic
Transaction data.
no setterinherited
dataMixInEnable → bool
Enable Data signal mixin
finalinherited
dataWidth → int
Width of the transaction data bus.
finalinherited
debugMixInEnable → bool
Enable Debug signal mixin
finalinherited
hashCode → int
The hash code for this object.
no setterinherited
id → Logic?
Identification tag for transaction.
no setterinherited
idMixInEnable → bool
Enable ID signal mixin
finalinherited
idUnq → Logic?
Coherency barrier.
no setterinherited
idWidth → int
Width of the ID signal.
finalinherited
last → Logic?
Indicates whether this is the last data transfer in a transaction.
no setterinherited
loop → Logic?
Loopback signal.
no setterinherited
loopWidth → int
Loopback signal width.
finalinherited
main → bool
Helper to control which direction the signals should be coming from.
finalinherited
modify ↔ String Function(String original)?
A function that can be used to modify all port names in a certain way.
getter/setter pairinherited
numRp → int
Number of resource planes.
finalinherited
pending → Logic?
Transfer might occur in the following cycle.
no setterinherited
persist → Logic?
Persist response.
no setterinherited
poison → Logic?
Indicator of data corruption on a given chunk.
no setterinherited
ports → Map<String, Logic>
Maps from the Interface's defined port name to an instance of a Logic.
no setterinherited
prefix → String
Prefix string for port declarations
finalinherited
ready → Logic?
Transfer is ready.
no setterinherited
resp → Logic?
Read response, indicates the status of a read transfer.
no setterinherited
responseMixInEnable → bool
Enable Response signal mixin
finalinherited
respWidth → int
Width of the RESP signal.
finalinherited
rp → Logic?
Indicator of resource plane.
no setterinherited
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
sharedCrd → Logic?
Transfer using a shared credit.
no setterinherited
sharedCredits → bool
Include shared crediting.
finalinherited
strb → Logic?
Write strobes, indicate which byte lanes hold valid data.
no setterinherited
strbWidth → int
Width of the strobe bus for data.
finalinherited
subInterfaces → Map<String, PairInterface>
A mapping from sub-interface names to instances of sub-interfaces.
no setterinherited
tag → Logic?
Tag.
no setterinherited
tagDataWidth → int
Width of data bus.
finalinherited
tagMatch → Logic?
Results of tag comparisons.
no setterinherited
tagMixInEnable → bool
Enable Tag signal mixin
finalinherited
tagUpdate → Logic?
Tags to update.
no setterinherited
trace → Logic?
Trace signal.
no setterinherited
tracePresent → bool
Trace present.
finalinherited
useBusy → bool
Include the BUSY signal.
finalinherited
useCrediting → bool
Should we use crediting.
finalinherited
useIdUnq → bool
Should the IDUNQ field be present.
finalinherited
useLast → bool
Controls the presence of last which is an optional port for multi burst transactions.
finalinherited
usePoison → bool
Controls the presence of POISON signal.
finalinherited
user → Logic?
User extension.
no setterinherited
userMixInEnable → bool
Enable User signal mixin
finalinherited
userWidth → int
Width of the USER signal.
finalinherited
useTag → bool
Use TAG signal.
finalinherited
useTagMatch → bool
Use TAGMATCH signal.
finalinherited
useTagUpdate → bool
Use TAGUPDATE signal.
finalinherited
valid → Logic
The transaction is valid.
no setterinherited

Methods

addSubInterface<PairInterfaceType extends PairInterface>(String name, PairInterfaceType subInterface, {bool reverse = false, String uniquify(String original)?}) → PairInterfaceType
Registers a new subInterface on this PairInterface, enabling a simple way to build hierarchical interface definitions.
inherited
clone() → Axi5LiteRChannelInterface
Copy Constructor.
override
conditionalDriveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → Conditional
Makes this conditionally drive interface signals tagged with tags on other.
inherited
conditionalReceiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → Conditional
Makes this signals tagged with tags be driven conditionally by other.
inherited
connectIO(Module module, Interface srcInterface, {Iterable<PairDirection>? inputTags, Iterable<PairDirection>? outputTags, Iterable<PairDirection>? inOutTags, String uniquify(String original)?}) → void
Calls Interface.connectIO for ports of this interface as well as hierarchically for all subInterfaces.
inherited
driveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this drive interface signals tagged with tags on other.
inherited
getPorts([Iterable<PairDirection>? tags]) → Map<String, Logic>
Returns all interface ports associated with the provided tags as a Map from the port name to the Logic port.
inherited
makeChunkPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeDataPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeDebugPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeIdPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeRespDataTagPorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeResponsePorts() → void
Helper to instantiate ACE specific request ports.
inherited
makeUserPorts() → void
Helper to instantiate ACE specific request ports.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
pairConnectIO(Module module, Interface<PairDirection> srcInterface, PairRole role, {String uniquify(String original)?}) → void
A simplified version of connectIO for PairInterfaces where by only specifying the role, the input and output tags can be inferred.
inherited
port(String name) → Logic
Accesses a port named name.
inherited
receiveOther(Interface<PairDirection> other, Iterable<PairDirection> tags) → void
Makes this signals tagged with tags be driven by other.
inherited
setPorts(List<Logic> ports, [Iterable<PairDirection>? tags]) → void
Adds a collection of ports to this Interface, each associated with all of tags.
inherited
toString() → String
A string representation of this object.
inherited
tryPort(String name) → Logic?
Provides the port named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool
The equality operator.
inherited