Cosim mixin

When applied to a ExternalSystemVerilogModule, will configure it so that it can be cosimulated in a SystemVerilog simulator along with the ROHD simulator.

Superclass constraints

Properties

acceptsEmptyPortConnections → bool
Indicates whether this module accepts empty port connections when being instantiated in SystemVerilog.
no setterinherited
compileArgs → List<String>?
A list of additional arguments to pass to compile phase of the SystemVerilog simulator.
no setter
cosimHierarchy → String
The hierarchy from the SystemVerilog cosimulation top to reach this module.
no setter
definitionName → String
The definition name of this Module used when instantiating instances in generated code.
no setterinherited
definitionParameters → List<SystemVerilogParameterDefinition>?
A collection of SystemVerilog SystemVerilogParameterDefinitions to be declared on the definition when generating SystemVerilog for this Module if generatedDefinitionType is DefinitionGenerationType.standard.
no setterinherited
expressionlessInputs → List<String>
A list of names of inputs which should not have any SystemVerilog expressions (including constants) in-lined into them. Only signal names will be fed into these.
finalinherited
extraArgs → List<String>?
A list of additional arguments to pass to both compile and execute phase of the SystemVerilog simulation.
no setter
filelists → List<String>?
A list of filelists (.f files) to pass to the compile stage.
no setter
generatedDefinitionType → DefinitionGenerationType
What kind of SystemVerilog definition this Module generates, or whether it does at all.
no setterinherited
hasBuilt → bool
Indicates whether this Module has had the build method called on it.
no setterinherited
hashCode → int
The hash code for this object.
no setterinherited
hierarchicalName → String
Returns the hierarchical name of this Module with the parent hierarchy included, separated by .s, e.g. top.mid.leaf. Because it depends on hierarchy, this is only valid after build has been called.
no setterinherited
inOuts → Map<String, Logic>
A map from inOut port names to this Module to corresponding Logic signals.
no setterinherited
inputs → Map<String, Logic>
A map from input port names to this Module to corresponding Logic signals.
no setterinherited
internalSignals → Iterable<Logic>
An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
no setterinherited
name → String
The name of this Module.
finalinherited
outputs → Map<String, Logic>
A map from output port names to this Module to corresponding Logic signals.
no setterinherited
parameters → Map<String, String>?
A map of parameter names and values to be passed to the SystemVerilog module.
finalinherited
parent → Module?
The parent Module of this Module.
no setterinherited
registreeName → String
The unique instance name for this registree in cosimulation.
no setter
reserveDefinitionName → bool
If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
finalinherited
reserveName → bool
If true, guarantees uniqueInstanceName matches name or else the build will fail.
finalinherited
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
signals → Iterable<Logic>
An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
no setterinherited
subModules → Iterable<Module>
An Iterable of all Modules contained within this Module.
no setterinherited
uniqueInstanceName → String
If this module has a parent, after build this will be a guaranteed unique name within its scope.
no setterinherited
verilogSources → List<String>?
A list of verilog source files to include in the build.
no setter

Methods

addInOut(String name, Logic source, {int width = 1}) → LogicNet
Registers a signal as an inOut to this Module and returns an inOut port that can be consumed inside this Module.
inherited
addInOutArray(String name, Logic source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an inOut LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addInput(String name, Logic source, {int width = 1}) → Logic
Registers a signal as an input to this Module and returns an input port that can be consumed.
inherited
addInputArray(String name, Logic source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an input LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addInterfacePorts<InterfaceType extends Interface<TagType>, TagType extends Enum>(InterfaceType source, {Iterable<TagType>? inputTags, Iterable<TagType>? outputTags, Iterable<TagType>? inOutTags, String uniquify(String original)?}) → InterfaceType
Connects the source to this Module using Interface.connectIO and returns a copy of the source that can be used within this module.
inherited
addOutput(String name, {int width = 1}) → Logic
Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it.
inherited
addOutputArray(String name, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an output LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addPairInterfacePorts<InterfaceType extends PairInterface>(InterfaceType source, PairRole role, {String uniquify(String original)?}) → InterfaceType
Connects the source to this Module using PairInterface.pairConnectIO and returns a copy of the source that can be used within this module.
inherited
addTypedInOut<LogicType extends Logic>(String name, LogicType source) → LogicType
Registers a signal as an inOut to this Module and returns an inOut port that can be consumed inside this Module. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
inherited
addTypedInput<LogicType extends Logic>(String name, LogicType source) → LogicType
Registers a signal as an input to this Module and returns an input port that can be consumed. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
inherited
addTypedOutput<LogicType extends Logic>(String name, LogicType logicGenerator({String name})) → LogicType
Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it. The type of the port will be LogicType and constructed via logicGenerator, which must properly update the name of the generated LogicType as well.
inherited
build() → Future<void>
Builds the Module and all subModules within it.
override
cosimRegister() → void
Registers the current Cosim module with the cosimulator for generation and cosimulation. Only registered modules will be cosimulated.
definitionVerilog(String definitionType) → String?
A custom SystemVerilog definition to be produced for this Module.
inherited
generateSynth() → String
Returns a synthesized version of this Module.
inherited
hierarchy() → Iterable<Module>
Returns an Iterable of Modules representing the hierarchical path to this Module.
inherited
hierarchyString([int indent = 0]) → String
Returns a pretty-print String of the heirarchy of all Modules within this Module.
inherited
inOut(String name) → Logic
Accesses the Logic associated with this Modules inOut port named name.
inherited
inOutSource(String name) → Logic
The original source provided to the creation of the inOut port name via addInOut or addInOutArray.
inherited
input(String name) → Logic
Accesses the Logic associated with this Modules input port named name.
inherited
inputSource(String name) → Logic
The original source provided to the creation of the input port name via addInput or addInputArray.
inherited
instantiationVerilog(String instanceType, String instanceName, Map<String, String> ports) → String
Generates custom SystemVerilog to be injected in place of a module instantiation.
inherited
isInOut(Logic signal) → bool
Returns true iff signal is the same Logic as the inOut port of this Module with the same name.
inherited
isInput(Logic signal) → bool
Returns true iff signal is the same Logic as the input port of this Module with the same name.
inherited
isOutput(Logic signal) → bool
Returns true iff signal is the same Logic as the output port of this Module with the same name.
inherited
isPort(Logic signal) → bool
Returns true iff signal is the same Logic as an input, output, or inOut port of this Module with the same name.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
output(String name) → Logic
Accesses the Logic associated with this Modules output port named name.
inherited
toString() → String
A string representation of this object.
inherited
tryInOut(String name) → Logic?
Provides the inOut named name if it exists, otherwise null.
inherited
tryInput(String name) → Logic?
Provides the input named name if it exists, otherwise null.
inherited
tryOutput(String name) → Logic?
Provides the output named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool
The equality operator.
inherited

Static Properties

logger → Logger?
An enablable logger (null if disabled) for Cosim related information.
no setter
registrees → Map<String, Cosim>
A collection of all registered Cosim modules.
no setter

Static Methods

connectCosimulation(CosimConfig cosimConfig) → Future<void>
Starts the SystemVerilog simulation and connects it to the ROHD simulator.
endCosim() → void
Passes an "END" message to Cosim as if it had been sent by the other simulator. This is helpful in cases where the simulator dies unexpectedly without gracefully notifying Cosim.
generateConnector({String directory = './', String pythonModuleName = defaultPythonModuleName, bool enableLogging = false}) → void
Generates collateral for building and executing a cosimulation.
reset() → Future<void>
Resets all context for cosimulation.

Constants

defaultPythonModuleName → const String
The default name of the python module containing the connector.