Cosim mixin - rohd_cosim library

Properties

verilogSources → List<String>?: A list of verilog source files to include in the build.
no setter
filelists → List<String>?: A list of filelists (.f files) to pass to the compile stage.
no setter
compileArgs → List<String>?: A list of additional arguments to pass to both compile phase of the SystemVerilog simulator.
no setter
extraArgs → List<String>?: A list of additional arguments to pass to both compile and execute phase of the SystemVerilog simulation.
no setter
cosimHierarchy → String: The hierarchy from the SystemVerilog cosimulation top to reach this module.
no setter
registreeName → String: The unique instance name for this registree in cosimulation.
no setter
parameters → Map<String, String>?: A map of parameter names and values to be passed to the SystemVerilog module.
finalinherited
name → String: The name of this Module.
finalinherited
reserveName → bool: If true, guarantees uniqueInstanceName matches name or else the build will fail.
finalinherited
reserveDefinitionName → bool: If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
finalinherited
parent → Module?: The parent Module of this Module.
no setterinherited
inputs → Map<String, Logic>: A map from input port names to this Module to corresponding Logic signals.
no setterinherited
outputs → Map<String, Logic>: A map from output port names to this Module to corresponding Logic signals.
no setterinherited
subModules → Iterable<Module>: An Iterable of all Modules contained within this Module.
no setterinherited
internalSignals → Iterable<Logic>: An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
no setterinherited
signals → Iterable<Logic>: An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
no setterinherited
uniqueInstanceName → String: If this module has a parent, after build this will be a guaranteed unique name within its scope.
no setterinherited
definitionName → String: The definition name of this Module used when instantiating instances in generated code.
no setterinherited
hasBuilt → bool: Indicates whether this Module has had the build() method called on it.
no setterinherited
hashCode → int: The hash code for this object.
no setterinherited
runtimeType → Type: A representation of the runtime type of the object.
no setterinherited
expressionlessInputs → List<String>: A list of names of inputs which should not have any SystemVerilog expressions (including constants) in-lined into them. Only signal names will be fed into these.
finalinherited

Methods

addInput(String name, Logic x, {int width = 1}) → Logic: Registers a signal as an input to this Module and returns an input port that can be consumed.
inherited
addInputArray(String name, Logic x, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Registers and returns an input LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addOutput(String name, {int width = 1}) → Logic: Registers an output to this Module and returns an output port that can be driven.
inherited
addOutputArray(String name, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Registers and returns an output LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
build() → Future<void>: Builds the Module and all subModules within it.
override
cosimRegister() → void: Registers the current Cosim module with the cosimulator for generation and cosimulation. Only registered modules will be cosimulated.
generateSynth() → String: Returns a synthesized version of this Module.
inherited
hierarchy() → Iterable<Module>: Returns an Iterable of Modules representing the hierarchical path to this Module.
inherited
hierarchyString([int indent = 0]) → String: Returns a pretty-print String of the heirarchy of all Modules within this Module.
inherited
input(String name) → Logic: Accesses the Logic associated with this Modules input port named name.
inherited
instantiationVerilog(String instanceType, String instanceName, Map<String, String> inputs, Map<String, String> outputs) → String: Generates custom SystemVerilog to be injected in place of a module instantiation.
inherited
isInput(Logic net) → bool: Returns true iff net is the same Logic as the input port of this Module with the same name.
inherited
isOutput(Logic net) → bool: Returns true iff net is the same Logic as the output port of this Module with the same name.
inherited
isPort(Logic net) → bool: Returns true iff net is the same Logic as an input or output port of this Module with the same name.
inherited
noSuchMethod(Invocation invocation) → dynamic: Invoked when a nonexistent method or property is accessed.
inherited
output(String name) → Logic: Accesses the Logic associated with this Modules output port named name.
inherited
toString() → String: A string representation of this object.
inherited
tryInput(String name) → Logic?: Provides the input named name if it exists, otherwise null.
inherited
tryOutput(String name) → Logic?: Provides the output named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool: The equality operator.
inherited

Static Properties

logger → Logger?: An enablable logger (null if disabled) for Cosim related information.
no setter
registrees → Map<String, Cosim>: A collection of all registered Cosim modules.
no setter

Static Methods

connectCosimulation(CosimConfig cosimConfig) → Future<void>: Starts the SystemVerilog simulation and connects it to the ROHD simulator.
endCosim() → void: Passes an "END" message to Cosim as if it had been sent by the other simulator. This is helpful in cases where the simulator dies unexpectedly without gracefully notifying Cosim.
generateConnector({String directory = './', String pythonModuleName = defaultPythonModuleName, bool enableLogging = false}) → void: Generates collateral for building and executing a cosimulation.
reset() → Future<void>: Resets all context for cosimulation.

Constants

defaultPythonModuleName → const String: The default name of the python module containing the connector.