Add a level 3 cache for all CPU sockets. The cache will be connected to all level 2 caches in the same CPU and therefore shared by all cores in the CPU. name can be given to set a name for the cache object in the hierarchy. line-size is cache line size (default 64 bytes), sets number of sets/indices, and ways number of ways (default 1).
You can configure the cache to be a write through cache by giving the -write-through flag, default is a write back cache.
To prevent the cache from allocating lines on writes use the -no-write-allocate flag.
The read-penalty, read-miss-penalty, write-penalty, write-miss-penalty sets the penalties in cycles for cache accesses and misses, respectively. The read/write penalty is added to the total penalty when accessing the cache (i.e., the cost of reaching the cache), a miss penalty is added when a miss occurs and there is no next level cache.
If prefetch-additional is given, the cache will prefetch additional consecutive cache lines on a miss.
-prefetch-adjacent means that the cache will, on a miss, prefetch the adjacent cache line as well, so the total fetch region is cache line size * 2, naturally aligned.
-ip-read-prefetcher and -ip-write-prefetcher adds a hardware instruction pointer based stride prefetcher for reads and writes respectively. Write prefetching will issue read for ownership prefetch accesses to the cache, meaning that other caches having those lines will be forced to flush them.