This device implements the external hardware needed for MS-DOS compatible handling of x87 exceptions. The circuit is normally part of the south bridge (for example the PIIX4). We have one input pin from the CPU, FERR#, which is asserted by the cpu when CR0.NE is clear + IGNNE# is low + a floating point exception condition is asserted. We have one output pin to the CPU, #IGNNE, which is raised by this device when FERR# is active and the port (normally F0h) is written. IGNNE is cleared when FERR is lowered. The output interrupt pin is raised when FERR, and is cleared by a write to the port. We provide the x87_ferr interface for the cpu to use, and the io-memory interface for the port. This device uses the x87_ignne interface to communicate the IGNNE status, and the simple-interrupt interface to connect to an interrupt controller.
conf_object, log_object, signal, io_memory
- cell-change
- Notifier that is triggered after the object's cell was changed.
- object-delete
- Notifier that is triggered just before Simics object is deleted.
- queue-change
- Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.
-
info
– print information about the object
-
status
– print status of the object
-
irq_dev
-
Required attribute;
read/write access; type:
o
Target interrupt device (typically a PIC).
-
irq_level
-
Required attribute;
read/write access; type:
i
Interrupt level (typically 13).
-
ignne_target
-
Required attribute;
read/write access; type:
o
Object to which the IGNNE line is connected (typically cpu0).
-
irq_status
-
Optional attribute;
read/write access; type:
i
The status of the output interrupt line.
-
ignne_status
-
Optional attribute;
read/write access; type:
i
The status of the output ignne line.
-
ferr_status
-
Optional attribute;
read/write access; type:
i
The status of the input ferr line.
x87_exception