The 8237x2 device implements the functionality of two cascaded 8237 DMA controllers. The 8237x2 supplies 7 dma channels that other devices can use for direct transfers to and from physical memory. The channel to use should be set in the device requesting DMA transfers. The 8237x2 exports two functions for reading and writing data. Limitation: Most registers in the 8237x2 device change hardware specific parameters. These do nothing in the 8237x2. Memory-to-Memory DMA transfers are not supported. The verify transfer type is not supported. Transfer delays are not modelled correctly, all transfers are completed in the same cycle as they are initiated by the device. Software initiated DMA requests are not supported.
conf_object, log_object, io_memory, legacy_dma
- cell-change
- Notifier that is triggered after the object's cell was changed.
- object-delete
- Notifier that is triggered just before Simics object is deleted.
- queue-change
- Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.
-
info
– print information about the object
-
status
– print status of the object
-
memory
-
Required attribute;
read/write access; type:
o
The physical memory to connect the DMA device to.
-
current_addr
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) The current address register. a1 - a4 are addresses of the first chip's 4 DMA channels' and b1 - b4 are for the second chip.
-
base_addr
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) The base address register for both chips' 4 DMA channels.
-
current_count
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) The current count register.
-
base_count
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) The base count register.
-
disabled
-
Optional attribute;
read/write access; type:
[ii]
(0|1,0|1) If the chips are disabled or enabled.
-
mask
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
(0|1, 0|1, 0|1, 0|1), (0|1, 0|1, 0|1, 0|1) Which channels are disables/enabled.
-
flip_flop
-
Optional attribute;
read/write access; type:
[ii]
(hi, lo) hi/lo byte access selector.
-
dec_address
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
(0|1, 0|1, 0|1, 0|1), (0|1, 0|1, 0|1, 0|1) If set decrement addresses on transfers instead of increment. Per channel.
-
auto_init
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
(0|1, 0|1, 0|1, 0|1), (0|1, 0|1, 0|1, 0|1) If set re-initialize registers at terminal count.
-
dma_type
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) DMA type 0 (verify), 1 (write), 2 (read), 3 (illegal) for all channels.
-
dma_mode
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) DMA mode 0 (demand), 1 (single), 2 (block), 3 (cascade) for all channels.
-
request
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) The request register.
-
tc
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
(0|1, 0|1, 0|1, 0|1), (0|1, 0|1, 0|1, 0|1) Bit set on terminal count (TC) for a DMA channel.
-
page_addr
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) The 64k/128k page that DMA is relative.
-
page_size
-
Optional attribute;
read/write access; type:
[ii]
(page-size1, page-size2) Page size for the controllers. 64k or 128k.
-
Optional attribute;
read/write access; type:
[[iiii]{2}]
((a1, a2, a3, a4), (b1, b2, b3, b4)) Extra page address registers. These registers have no function in the device.
8237x2