i21554-prim

Description

The Intel® i21554-prim models the primary interface on the PCI to PCI bridge

Interfaces Implemented

conf_object, log_object, bridge, pci_device, io_memory

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Attributes

base_translate: Optional attribute; read/write access; type: [i{6}]
Translation bases.
base_setup: Optional attribute; read/write access; type: [i{7}]
The setup register values. The i21554 device can be programmed by an on board serial prom that will initialize the setup registers. In Simics this is done by setting this attribute. The seven registers are in the following order: downstream memory 0, downstream I/O / memory 1, downstream memory 2, downstream memory 3 (lower), downstream memory 3 (upper), upstream I/O / memory 0 and upstream memory 1.
scnd_interface: Required attribute; read/write access; type: o
Secondary interface object for the bridge
bridge_mappings: Optional attribute; read/write access; type: [[iiii]*]
List of all current PCI I/O and memory mappings.
down_conf_addr: Optional attribute; read/write access; type: i
Downstream configuration address register.
chip_control0: Optional attribute; read/write access; type: i
Chip Control 0 register.
pci_bus: Optional attribute; read/write access; type: o|n
The PCI bus this device is connected to, implementing the pci-bus interface.
interrupt_pin: Optional attribute; read/write access; type: [iiii]
State of the interrupt pin.
config_registers: Optional attribute; read/write access; type: [i{64}]
The 64 PCI configuration registers, each 32 bits in size.
write_masks: Optional attribute; read/write access; type: [[ii]*]
Write masks for all registered configuration registers. The format for each entry is (offset, mask).
mappings: Optional attribute; read/write access; type: [[i{5:8}]|[iiiiiiiio|nii]*]
List of all current PCI IO and memory mappings.
expansion_rom: Optional attribute; read/write access; type: n|[oii]
ROM object, map size, and map function number for the Expansion ROM.
config_register_info: Pseudo attribute; read-only access; type: [[isii]*]
Register info for all registered configuration registers. The format for each entry is (offset, name, size, write-mask).

Provided By

i21554