g-cache

Description

g-cache is an in-order 'flat' cache model with the following features: configurable number of lines, line size, associativity; indexing/tagging on physical/virtual addresses; configurable policies for write-allocate and write-back; random, cyclic and lru replacement policies; several caches can be chained; a single cache can be connected to several processors; support for a simple MESI protocol between caches.

It is imperative to start Simics with the -stall flag to get correct cache statistics. It is possible to start Simics without it, but no transactions will then be stalled, and all transaction may not be visible to the cache.

Note that the sample MESI protocol was written to handle simple cases such as several L1 write-through caches with L2 caches synchronizing via MESI. To model more complex protocols, you will need to modify g-cache.

See Simics Analyzer User's Guide for more information.

Interfaces Implemented

conf_object, log_object, mesi_listen_interface, timing_model, cache_control

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Commands for this class

add-profiler – add a profiler to the cache
info – print information about the object
line-status – print the cache lines status
remove-profiler – remove a profiler from the cache
reset-cache-lines – reset all the cache lines
reset-statistics – reset the cache statistics
statistics – print the cache statistics
status – print status of the object

Attributes

cpus: Required attribute; read/write access; type: n|o|[o*]
cpus that can send transactions to the cache.
config_line_number: Optional attribute; read/write access; type: i
Number of lines in the cache (default is 128)
config_line_size: Optional attribute; read/write access; type: i
Cache line size (must be a power of 2, default is 32). If you plan to use the STC in combination to improve the cache performance, this value must be greater or equal to the instruction_profile_line_size.
config_assoc: Optional attribute; read/write access; type: i
Cache associativity. Note that the total number of lines divided by the associativity must be a power of 2. (default is 4).
config_virtual_index: Optional attribute; read/write access; type: i
Address used to compute the set in the cache (0: physical, 1: virtual; default is 0).
config_virtual_tag: Optional attribute; read/write access; type: i
Address used to compute the tag of the cache line (0: physical, 1: virtual; default is 0).
config_write_allocate: Optional attribute; read/write access; type: i
Write allocation policy (0: non-write allocate, 1: write-allocate, default is 0).
config_write_back: Optional attribute; read/write access; type: i
Write policy (0: write-through, 1: write-back, default is 0).
config_replacement_policy: Optional attribute; read/write access; type: s
Replacement policy ("random", "lru" or "cyclic", default is "random").
penalty_read: Optional attribute; read/write access; type: i
Stall penalty (in cycles) for any incoming read transaction. A cache-hit on read will only suffer a 'read' penalty (default is 0). Note that if you set this to a non-zero value, the simulation won't be able to use the STCs.
penalty_write: Optional attribute; read/write access; type: i
Stall penalty (in cycles) for any incoming write transaction. A cache-hit on write (in a write-back cache) will only suffer a 'write' penalty (default is 0). Note that if you set this to a non-zero value, the simulation won't be able to use the STCs.
stat_transaction: Optional attribute; read/write access; type: i
Total number of transactions seen by the cache.
stat_dev_data_read: Optional attribute; read/write access; type: i
Number of device data read transactions (DMA).
stat_dev_data_write: Optional attribute; read/write access; type: i
Number of device data write transactions (DMA).
stat_c_dev_data_read: Optional attribute; read/write access; type: i
Number of cached device data read transactions (DMA).
stat_c_dev_data_write: Optional attribute; read/write access; type: i
Number of cached device data write transactions (DMA).
stat_uc_data_read: Optional attribute; read/write access; type: i
Number of uncacheable data read transactions.
stat_uc_data_write: Optional attribute; read/write access; type: i
Number of uncacheable data write transactions.
stat_uc_inst_fetch: Optional attribute; read/write access; type: i
Number of uncacheable inst fetch transactions.
stat_data_read: Optional attribute; read/write access; type: i
Number of cacheable data read transactions (may be underestimated if the STCs are used, see Simics Analyzer Guide for more information).
stat_data_read_miss: Optional attribute; read/write access; type: i
Number of cacheable data read transactions that missed in the cache.
stat_data_write: Optional attribute; read/write access; type: i
Number of cacheable data write transactions (may be underestimated if the STCs are used, see Simics Analyzer Guide for more information).
stat_data_write_miss: Optional attribute; read/write access; type: i
Number of cacheable data write transactions that missed in the cache (write-through caches report a correct miss value but all writes are sent to the next level).
stat_inst_fetch: Optional attribute; read/write access; type: i
Number of cacheable instruction fetches (may be underestimated if the STCs are used, see Simics Analyzer Guide for more information).
stat_inst_fetch_miss: Optional attribute; read/write access; type: i
Number of cacheable instruction fetches that missed in the cache.
stat_copy_back: Optional attribute; read/write access; type: i
Number of copy-back transactions initiated by the cache.
timing_model: Optional attribute; read/write access; type: o|n
Object listening on transactions coming from the cache (line fetch, copy-back).
profilers: Pseudo attribute; read/write access; type: [o|n*]
Profilers connected to the cache.
config_block_STC: Optional attribute; read/write access; type: i
Prevent the cache from using the STCs. Read the 'Cache Simulation' chapter in Simics Analyzer Guide for more information (0: STC usage allowed, 1: STC usage blocked; default is 0).
penalty_read_next: Optional attribute; read/write access; type: i
Stall penalty (in cycles) for a read transaction issued by the cache to the next level cache. A cache miss on read will have a penalty for 'read' (incoming transaction) + 'read-next' (line fetch transaction) + any penalty set by the next caches. (default is 0)
penalty_write_next: Optional attribute; read/write access; type: i
Stall penalty (in cycles) for a write transactions issued by the cache to the next level cache. In a write-back cache, a cache miss on read triggering a copy-back transaction will have a penalty for 'read', 'write-next' (copy-back transaction) and 'read-next' (line fetch transaction). In write-through cache, a write transaction will always have at least a penalty for 'write' and 'write-next' (write-through transaction). (default is 0).
lines: Optional attribute; read/write access; type: [[iiii]*]
Content of the cache lines
cacheable_devices: Optional attribute; read/write access; type: n|[o*]
List of devices that can be cached.
snoopers: Optional attribute; read/write access; type: n|[o*]
Caches listening on the bus (MESI protocol).
higher_level_caches: Optional attribute; read/write access; type: n|[o*]
Higher level caches that need to receive invalidates during MESI snooping (MESI protocol).
stat_mesi_exclusive_to_shared: Optional attribute; read/write access; type: i
Number of Exclusive to Shared transitions in MESI protocol.
stat_mesi_modified_to_shared: Optional attribute; read/write access; type: i
Number of Modified to Shared transitions in MESI protocol.
stat_mesi_invalidate: Optional attribute; read/write access; type: i
Number of lines invalidated in MESI protocol.
stat_lost_stall_cycles: Optional attribute; read/write access; type: i
Stall cycles lost due to non-stallable transactions.
config_seed: Optional attribute; read/write access; type: i
Seed for random replacement policy, default is 0).
lines_last_used: Optional attribute; read/write access; type: [i*]
Last used timestamp for the cache lines
next_line_in_set: Optional attribute; read/write access; type: [i*]
Next line used for replacement in a given set.

Provided By

g-cache