clock

Description

The clock class can be used to drive the simulation when there is no processor in the system. It implements the cycle interface, which means that devices and other objects can post events on it to be executed at a later time. The clock frequency determines the length of a clock cycle, which is used as the granularity for executing events. It is not possible to post step events to the clock.

Interfaces Implemented

conf_object, log_object, execute, frequency_listener, frequency, concurrency_mode, execute_control, cycle

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
frequency-change: Notifier that is triggered when frequency changes. New frequency can be read via the frequency interface of the object.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Port Objects

vtime: vtime – event handler
vtime.cycles: cycle-counter – cycle queue
vtime.ps: ps-clock – event queue (ps)

Commands for this class

info – print information about the object
status – print status of the object

Commands for interface cycle

bp-break-cycle – set cycle breakpoint
bp-break-time – set time breakpoint
bp-run-until-cycle – run until specified cycle
bp-run-until-time – run until specified time
bp-trace-cycle – enable tracing of cycle points
bp-trace-time – enable tracing of time points
bp-wait-for-cycle – wait for specified cycle
bp-wait-for-time – wait for specified time
cycle-break – deprecated set cycle breakpoint
cycle-break-absolute – deprecated set absolute cycle breakpoint
print-time – print number of steps and cycles executed
wait-for-cycle – deprecated wait until reaching cycle
wait-for-time – deprecated wait until reaching a specified time

Attributes

freq_mhz: Required attribute; read/write access; type: i|f
Clock frequency in MHz.
cycles: Optional attribute; read/write access; type: i
Time measured in cycles from machine start.
time_queue: Pseudo attribute; read/write access; type: [[osaai]*]
((object, evclass, value, slot, when)*). Pending cycle queue events.
multicore_accelerator_enabled: Pseudo attribute; read/write access; type: b
If TRUE the clock enabled for Multicore Accelerator execution, otherwise FALSE
mca_concurrency_mode: Optional attribute; read/write access; type: i
Multicore Accelerator mode used by processor. One of Sim_Concurrency_Mode_Serialized (1), Sim_Concurrency_Mode_Serialized_Memory (2), or Sim_Concurrency_Mode_Full (4)
stop_listeners: Optional attribute; read/write access; type: [[o,n|s]*]
List of objects listening for stop signal. Each object/port pair needs to implement the pulse interface through which the information to stop will be signaled. Port can be NIL in which case the pulse interface will be used without a port.
do_not_schedule: Optional attribute; read/write access; type: b
Set to TRUE to prevent this object from being scheduled by the cell.
cell: Optional attribute; read/write access; type: o|n
Cell

Provided By

clock