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Simics Reference Manual  /  5 Classes  / 

cell

Description

A simulation cell, representing an autonomous partition of the configuration and able to be simulated in parallel with other cells. See the "Multithreading" section in the Introduction chapter of the API Reference Manual.

Interfaces Implemented

conf_object, log_object, temporal_state, link_route, dist_control_node, concurrency_group, breakpoint_trigger, cell_inspection, sync_node

Notifiers

cell-change
Notifier that is triggered after the object's cell was changed.
object-delete
Notifier that is triggered just before Simics object is deleted.
queue-change
Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Port Objects

ps
ps-clock – ps clock

Commands for this class

Attributes

schedule_list
Optional attribute; read/write access; type: [o*]
Execute objects that belong to the cell, in scheduling order
clocks
Pseudo attribute; read-only access; type: [o*]
Clock objects that belong to the cell.
scheduled_object
Optional attribute; read/write access; type: n|o
Currently scheduled object for this cell
current_processor
Optional attribute; read/write access; type: n|o
Current processor in this cell
current_step_obj
Optional attribute; read/write access; type: n|o
Current step queue in this cell
current_cycle_obj
Pseudo attribute; read/write access; type: n|o
Current cycle queue in this cell
time_quantum
Pseudo attribute; read/write access; type: f
Length of the time quantum in seconds, or 0 if not specified.
time_quantum_ps
Optional attribute; read/write access; type: i
Length of the time quantum in picoseconds, or 0 if not specified.
machine_sync_events
Optional attribute; read/write access; type: [[osaai]*]
((object, evclass, value, obsolete when)*). Pending machine sync events.
sync_domain
Optional attribute; read/write access; type: o
Synchronization domain for this cell
leader
Optional attribute; read/write access; type: o|n
Leader object
max_time_span_ps
Optional attribute; read/write access; type: i
Upper limit of the allowed global time difference for CPUs simulated simultaneously using multiple host threads, or 0 if no limit is desired.

Provided By

Simics Core
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