apic

Description

The APIC class implements the functionality of the local (on-chip) APIC that is part of the Intel® Architecture and was first implemented in the Pentium® processor. Each APIC instance is connected to an I/O-APIC through the APIC bus (multiple I/O-APIC systems are not supported). Reference: Intel Architecture Software Developer's Manual Volume 3.

Interfaces Implemented

conf_object, log_object, io_memory, apic_cpu, interrupt_cpu, int_register, apic_timer, apic_bus_to_apic

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Commands for this class

info – print information about the object
status – print status of the object

Attributes

apic_id: Required attribute; read/write access; type: i
APIC ID.
apic_bus: Required attribute; read/write access; type: o
Bus implementing the apic-bus interface.
version: Optional attribute; read/write access; type: i
APIC Version.
apic_type: Optional attribute; read/write access; type: s
APIC Type ("P6", "P4" or "X2")
cpu: Required attribute; read/write access; type: o
Target processor implementing the X86 and PROCESSOR_INFO_V2 interfaces. The APIC will assume ownership of the APICBASE MSR if the processor implements the X86_MSR interface. If the processor does not implement the X86_MSR interface, then the APIC needs to be mapped and potentially moved by some other logic.
task_priority: Optional attribute; read/write access; type: i
Task priority register.
logical_destination: Optional attribute; read/write access; type: i
Logical destination register.
destination_format: Optional attribute; read/write access; type: i
Destination format register.
spurious_interrupt_vector: Optional attribute; read/write access; type: i
Spurious interrupt vector register.
interrupt_command: Optional attribute; read/write access; type: i
Interrupt command register (all 64 bits).
lvt_timer: Optional attribute; read/write access; type: i
Local vector table, timer.
lvt_lint0: Optional attribute; read/write access; type: i
Local vector table, local interrupt 0.
lvt_lint1: Optional attribute; read/write access; type: i
Local vector table, local interrupt 1.
lvt_error: Optional attribute; read/write access; type: i
Local vector table, error.
lvt_performance_counter: Optional attribute; read/write access; type: i
Local vector table, performance counter.
lvt_thermal_sensor: Optional attribute; read/write access; type: i
Local vector table, thermal sensor.
initial_count: Optional attribute; read/write access; type: i
Initial count register for timer.
divisor_ln_2: Optional attribute; read/write access; type: i
Log2 of timer divisor. Note that this is not the format used in the divide configuration register.
count_in_progress: Optional attribute; read/write access; type: i
Count is in progress.
count_initial: Optional attribute; read/write access; type: i
Initial count when timer was started.
count_start: Optional attribute; read/write access; type: i
Local CPU time when count was started.
ext_int_obj: Optional attribute; read/write access; type: o|n
Object pending with delivery mode ExtINT.
cpu_bus_divisor: Optional attribute; read/write access; type: f
Divisor between CPU frequency and bus frequency used by the APIC timer.
status: Optional attribute; read/write access; type: [[i{3}]{256}]
((tm0, ir0, is0), ..., (tm255, ir255, is255)). Status registers.
priority: Optional attribute; read/write access; type: [[[ii]{2}]{16}]
(((state, vector){2}){16}). Interrupt slots.
arbitration_id: Optional attribute; read/write access; type: i
Arbitration ID.
error_status: Optional attribute; read/write access; type: i
Error status.
remote_read: Optional attribute; read/write access; type: i
Remote read.
interrupt_posted: Optional attribute; read/write access; type: i
Interrupt signal raised.
physical_broadcast_address: Optional attribute; read/write access; type: i
Current broadcast address for interprocessor interrupts and interrupts from the I/O-APIC. Default value is FFh (0Fh for Pentium® (classic) family or P6 family processors); FFFFFFFFh in x2APIC mode
apicbase_msr: Optional attribute; read/write access; type: n|i
APICBASE MSR. Should be Nil if and only if the bound CPU does not implement the X86_MSR interface.

Provided By

apic