DS323x M25Pxx
Simics Reference Manual  /  5 Classes  / 

ISA

Description

The ISA device models the industry standard architecture bus present in most PCs. It is responsible for dispatching interrupts to the interrupt controllers (I/O-APIC and/or PIC). The operating system must make sure that interrupts are not handled by both interrupt controllers either by disabling one of the controllers or by masking interrupts in at least one of the controllers.

Interfaces Implemented

conf_object, log_object, simple_interrupt

Notifiers

cell-change
Notifier that is triggered after the object's cell was changed.
object-delete
Notifier that is triggered just before Simics object is deleted.
queue-change
Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Commands for this class

Attributes

pic
Required attribute; read/write access; type: o
The programmable interrupt controller attached to. Must implement the simple_interrupt interface.
ioapic
Optional attribute; read/write access; type: o|n
The advanced programmable interrupt controller attached to. Must implement the ioapic interface.
irq_to_pin
Optional attribute; read/write access; type: [i{32}]
(i0, i1, ..., i31) Entry in specifies which pin irq n is attached to.
irq_status
Optional attribute; read/write access; type: [i{32}]
(i0, i1, ..., i31) Entry in specifies the current status for input interrupt pin i, 1 for active and 0 for inactive.

Provided By

isa
DS323x M25Pxx