integer.
Number of implemented ASID bits.Maximum value for ASIDLEN is 9 for Sv32 and 16 for Sv39, Sv48 and Sv57[[o,i]*].
((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.
This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.
boolean.
Enables automatic detection of loops which can be hypersimulated.[[iis]*].
{ffwd_steps, addr, precond} Information on automatically found hypersim loops.[os], object, or nil.
CLINT target. Access to the CLINT are done via the io_memory interface.[iiiii].
Core internal clic interrupt stateinteger.
Time measured in cycles from machine start.boolean.
Set to TRUE to prevent this object from being scheduled by the cell.boolean.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.[[o|n,s,i]*].
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).boolean.
If set to False, the core handles MMU page access flags update in hardware, if set to True page fault exceptions are raised when flags needs to be updated by software.boolean.
If set to False, the core handles unaligned data accesses internally without exception. If set to True unaligned data accesses will cause exceptions.[iii].
Exclusive lock for atomic instructions LR and SCboolean.
Standard Extension for Atomic Instructionsboolean.
Standard Extension for Atomic Instructionsboolean.
Standard Extension for Double-Precision Floating-Pointboolean.
Standard Extension for Single-Precision Floating-Pointboolean.
RV32I or RV32E Base Instruction Set.boolean.
Standard Extension for Integer Multiplication and Divisionboolean.
Bit-Manipulation ISA-extension, Address generation instructionsboolean.
Bit-Manipulation ISA-extension, Basic bit-manipulationboolean.
Bit-Manipulation ISA-extension, Carry-less multiplicationboolean.
Bit-Manipulation ISA-extension, Single-bit instructions[b*].
State of the external signalsinteger.
Floating-Point Control and Status Register (frm + fflags)[i{32}].
(f0, f1, ..., f31) Floating-point registersfloat.
Maximum allowed value for the number of instructions executed per virtual second, expressed as a fraction of the current CPU frequency.float.
Minimum allowed value for the number of instructions executed per virtual second, expressed as a fraction of the current CPU frequency.float.
Freerun speed. A value of 1.0 means realtime.float or integer.
Processor clock frequency in MHz.[ii], [os], or object.
Processor clock frequency in Hz, as a rational number [numerator, denominator], or as a frequency provider implementing the frequency. The legacy simple_dispatcher is also supported.[i{32}].
(r0, i1, ..., r31) General purpose registersinteger.
Hypervisor mode supported in the cpuboolean.
If TRUE, the model will keep trying to cache memory through direct memory even if it fails.integer.
Instructions-retired counter for RDINSTRET instructioninteger.
Status of the core's internal interrupts.integer.
Current interrupt pending or -1 if no interrupt is pending.boolean.
TRUE if the processor is currently stalling by request of a timing-model.[[sb]*].
List of available ISA-variants coupled with if they are enabled or not. To be able to use a variant the corresponding extension also needs to be supported and enabled.
Note, isa_variants are not affected by reset.string.
MP protocol. One of {'msi', 'ww', 'wwp'}integer.
Multicore Accelerator mode used by processor. One of Sim_Concurrency_Mode_Serialized (1), Sim_Concurrency_Mode_Serialized_Memory (2), or Sim_Concurrency_Mode_Full (4)integer.
Machine Configuration Pointer Registerinteger.
Machine environment configuration registerinteger.
Machine performance-monitoring counter 10integer.
Machine performance-monitoring counter 11integer.
Machine performance-monitoring counter 12integer.
Machine performance-monitoring counter 13integer.
Machine performance-monitoring counter 14integer.
Machine performance-monitoring counter 15integer.
Machine performance-monitoring counter 16integer.
Machine performance-monitoring counter 17integer.
Machine performance-monitoring counter 18integer.
Machine performance-monitoring counter 19integer.
Machine performance-monitoring counter 20integer.
Machine performance-monitoring counter 21integer.
Machine performance-monitoring counter 22integer.
Machine performance-monitoring counter 23integer.
Machine performance-monitoring counter 24integer.
Machine performance-monitoring counter 25integer.
Machine performance-monitoring counter 26integer.
Machine performance-monitoring counter 27integer.
Machine performance-monitoring counter 28integer.
Machine performance-monitoring counter 29integer.
Machine performance-monitoring counter 3integer.
Machine performance-monitoring counter 30integer.
Machine performance-monitoring counter 31integer.
Machine performance-monitoring counter 4integer.
Machine performance-monitoring counter 5integer.
Machine performance-monitoring counter 6integer.
Machine performance-monitoring counter 7integer.
Machine performance-monitoring counter 8integer.
Machine performance-monitoring counter 9integer.
Machine performance-monitoring event selector 10integer.
Machine performance-monitoring event selector 11integer.
Machine performance-monitoring event selector 12integer.
Machine performance-monitoring event selector 13integer.
Machine performance-monitoring event selector 14integer.
Machine performance-monitoring event selector 15integer.
Machine performance-monitoring event selector 16integer.
Machine performance-monitoring event selector 17integer.
Machine performance-monitoring event selector 18integer.
Machine performance-monitoring event selector 19integer.
Machine performance-monitoring event selector 20integer.
Machine performance-monitoring event selector 21integer.
Machine performance-monitoring event selector 22integer.
Machine performance-monitoring event selector 23integer.
Machine performance-monitoring event selector 24integer.
Machine performance-monitoring event selector 25integer.
Machine performance-monitoring event selector 26integer.
Machine performance-monitoring event selector 27integer.
Machine performance-monitoring event selector 28integer.
Machine performance-monitoring event selector 29integer.
Machine performance-monitoring event selector 3integer.
Machine performance-monitoring event selector 30integer.
Machine performance-monitoring event selector 31integer.
Machine performance-monitoring event selector 4integer.
Machine performance-monitoring event selector 5integer.
Machine performance-monitoring event selector 6integer.
Machine performance-monitoring event selector 7integer.
Machine performance-monitoring event selector 8integer.
Machine performance-monitoring event selector 9integer.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).integer.
Supported MMU mode.Valid modes are: 0 (Bare), 1 (Sv32)integer.
Scratch register for machine trap handlersinteger.
Machine security configuration registerinteger.
Additional machine security conf. registerboolean.
Multicore Accelerator enabled for processor.boolean.
If true, the processor is disabled by explicit user action and will not execute instructions until re-enabled by user. No architectural transitions, such as resets, will re-enable it on their own.integer.
Number of PMP address registers in this core[i|[ii]|[iii]*].
((address, length, hits)*).Core_Address_Not_Mapped hap.object.
Physical memory space. Must implement memory-space, breakpoint and breakpoint_query interfaces.integer.
Physical memory protection address register 0integer.
Physical memory protection address register 1integer.
Physical memory protection address register 10integer.
Physical memory protection address register 11integer.
Physical memory protection address register 12integer.
Physical memory protection address register 13integer.
Physical memory protection address register 14integer.
Physical memory protection address register 15integer.
Physical memory protection address register 2integer.
Physical memory protection address register 3integer.
Physical memory protection address register 4integer.
Physical memory protection address register 5integer.
Physical memory protection address register 6integer.
Physical memory protection address register 7integer.
Physical memory protection address register 8integer.
Physical memory protection address register 9integer.
Physical memory protection configuration 0integer.
Physical memory protection configuration 1integer.
Physical memory protection configuration 11integer.
Physical memory protection configuration 13integer.
Physical memory protection configuration 15integer.
Physical memory protection configuration 2integer.
Physical memory protection configuration 3integer.
Physical memory protection configuration 5integer.
Physical memory protection configuration 7integer.
Physical memory protection configuration 9integer.
Simics internal number for an instance of the 'processor_info' interface. Each instance must have a unique number. This attribute can only be set as part of an initial configuration.boolean.
Controls if fprs will be cleared at resetboolean.
Controls if gprs will be cleared at resetboolean.
Controls if all csrs will be reset to startup value at resetinteger.
Address core starts executing from after resetinteger.
Supervisor address translation and protectionobject or nil.
This is the main program memory-space shared with other processors. In the chain of memory-spaces starting from the physical_memory attribute, this is the first memory-space that also is accessible by other processors. A value of Nil means the physical_memory attribute is used as main program memory-space.integer.
Status of the core's external signals.integer.
The simulation mechanism used for the processor. One of the values of the simulation_mode_t enum.integer.
Scratch register for supervisor trap handlersinteger.
The number of cycles the processor will stall[iii].
If is_stalling is set, this contains information about the current memory operation.string.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.[[o|n,s,a,s,i]*].
((object, evclass, value, slot, step)*). Pending step queue events.integer.
Number steps executed since machine start.integer.
Supervisor mode supported in the cpu[[o|n,s,a,s|n,i]*].
((object, evclass, value, slot, cycle)*). Pending time queue events.boolean.
If set to False, the core handles the RDTIME and RDTIMEH in hardware, if set to True an illegal instruction is raised.integer.
User mode supported in the cpu[os], object, or nil.
Target to raise or lower a signal to when core goes into wait for interrupt state. Object must implement the signal interface. A signal will be raised when wfi instruction is executed and not interrupt is active. The signal will be lowered when the CPU resumes execution. The signal will be lowered when the CPU is resetinteger.
Controls which bits in the misa csr that can be written by instructions. Default is 0.
string.
Implemented architecture (risc-v)
| aprof-views | manipulate list of selected address profiling views |
| info | print information about the object |
| print-page-table | print page table entries |
| status | print status of the object |