2.3 Global Commands

break-vmread

Synopsis

break-vmread (field|-all|-list)
<x86>.break-vmread (field|-all|-list)
<x86>.unbreak-vmread (field|-all|-list)
unbreak-vmread (field|-all|-list)

Description

Enables and disables breaking simulation on Intel® Virtual Machine Control Structure (Intel ® VMCS) reads. When this is enabled, every time the specified VMCS field is read during simulation a message is printed. The message will name the VMCS field being read, and the value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable breaking simulation on all VMCS fields.

Using the -list argument will print out the VMCS fields accesses on which a breakpoint will trigger.

The non-namespace variant of this command breaks the simulation on VMCS field reads on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

trace-vmread, break-vmwrite

break-vmwrite

Synopsis

break-vmwrite (field|-all|-list)
<x86>.break-vmwrite (field|-all|-list)
<x86>.unbreak-vmwrite (field|-all|-list)
unbreak-vmwrite (field|-all|-list)

Description

Enables and disables breaking simulation on Intel® Virtual Machine Control Structure (Intel ® VMCS) updates. When this is enabled, every time the specified VMCS field is updated during simulation a message is printed. The message will name the VMCS field being read, and the new value. The new value will be printed even if it is identical to the previous value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable breaking simulation on all VMCS fields.

Using the -list argument will print out the VMCS fields accesses on which a breakpoint will trigger.

The non-namespace variant of this command breaks the simulation on VMCS field updates on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

trace-vmwrite, trace-vmread

create-chassis-qsp-x86

Synopsis

create-chassis-qsp-x86 ["name"]

Description

This command creates a non-instantiated component of the class chassis_qsp_x86.

The class description for the chassis_qsp_x86 class: Chassis for QSP x86 systems.

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

x58-ich10-comp

create-chassis-x58-ich10

Synopsis

create-chassis-x58-ich10 ["name"]

Description

This command creates a non-instantiated component of the class chassis_x58_ich10.

The class description for the chassis_x58_ich10 class: Chassis for Intel® X58-ICH10 systems.

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

x58-ich10-comp

create-leds-and-button-panel

Synopsis

create-leds-and-button-panel ["name"]

Description

This command creates a non-instantiated component of the class leds_and_button_panel.

The class description for the leds_and_button_panel class: The system panel to display the front end of the LEDs and button device.

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

sc-leds-and-button-pcie-dev

create-motherboard-x58-ich10

Synopsis

create-motherboard-x58-ich10 ["name"] [acpi] ["apic_bus_class"] ["bios"] [break_on_reboot] ["lan_bios"] ["mac_address"] ["rtc_time"] ["spi_flash"] [system_clock] ["system_clock_class"]

Description

This command creates a non-instantiated component of the class motherboard_x58_ich10.

The class description for the motherboard_x58_ich10 class: Motherboard with Intel® X58 Express Chipset (northbridge) and Intel® ICH10 (southbridge).

name is Optional

If not specified, the component will get a class-specific default name.

acpi is Optional

Use ACPI when True, default value is True.

apic_bus_class is Optional

APIC bus classname

bios is Optional

The x86 BIOS file to use.

break_on_reboot is Optional

If true, the simulation will stop when machine is rebooted.

lan_bios is Optional

The Expansion ROM BIOS file for the ICH10 LAN.

mac_address is Optional

MAC address

rtc_time is Optional

The date and time of the Real-Time clock. Please note that time-zone information is not supported and will be silently dropped when passed to the RTC object.

spi_flash is Optional

The ICH10 SPI flash file to use.

system_clock is Optional

If true, the motherboard will contain a clock separate from the processor, which will be used as queue for all devices. The class used for the clock is taken from system_clock_class.

system_clock_class is Optional

The class used for the system_clock.

Provided By

x58-ich10-comp

create-processor-core-i7

Synopsis

create-processor-core-i7 ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_core_i7.

The class description for the processor_core_i7 class: Intel® Core™ i7 processor.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-core-i7-6c-2t

Synopsis

create-processor-core-i7-6c-2t ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_core_i7_6c_2t.

The class description for the processor_core_i7_6c_2t class: Intel® Core™ i7 processor with 6 cores and 2 threads.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-core-i7-8c-4t

Synopsis

create-processor-core-i7-8c-4t ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_core_i7_8c_4t.

The class description for the processor_core_i7_8c_4t class: Intel® Core™ i7 processor with 8 cores and 4 threads.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-core-i7-duo

Synopsis

create-processor-core-i7-duo ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_core_i7_duo.

The class description for the processor_core_i7_duo class: Intel® Core™ i7 processor with 1 core a and 2 threads.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-core-i7-single

Synopsis

create-processor-core-i7-single ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_core_i7_single.

The class description for the processor_core_i7_single class: Intel® Core™ i7 processor with just one core and one thread.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-x86-intel64

Synopsis

create-processor-x86-intel64 ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_x86_intel64.

The class description for the processor_x86_intel64 class: Intel® Extendable 64-bit processor.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-x86QSP1

Synopsis

create-processor-x86QSP1 ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_x86QSP1.

The class description for the processor_x86QSP1 class: x86-64 QSP processor with variable number of cores and threads.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-xeon-5500

Synopsis

create-processor-xeon-5500 ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_xeon_5500.

The class description for the processor_xeon_5500 class: Intel® Xeon® 5500 processor.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-processor-xeon-5530

Synopsis

create-processor-xeon-5530 ["name"] [apic_freq_mhz] [cpi] [freq_mhz] [n_cores] [n_threads] [package_number] [use_vmp]

Description

This command creates a non-instantiated component of the class processor_xeon_5530.

The class description for the processor_xeon_5530 class: Intel® Xeon® E5530 processor with 4 cores and 2 threads.

name is Optional

If not specified, the component will get a class-specific default name.

apic_freq_mhz is Optional

APIC bus frequency in MHz, default is 10 MHz.

cpi is Optional

Cycles per instruction.

freq_mhz is Optional

Processor frequency in MHz, default is 10 MHz.

n_cores is Optional

Quantity of CPU cores

n_threads is Optional

Quantity of threads per 1 CPU core

package_number is Optional

CPU package identification number

use_vmp is Optional

Enable VMP at setup by setting attribute to True, disable VMP at setup by setting attribute to False. The attribute can be changed at run-time but the setting will only affect the threads in the component at instantiation. This option affects simulated time. See the performance chapter in the Simics User's Guide for more information about VMP.

Provided By

x86-nehalem-comp

create-sc-leds-and-button-pcie-comp

Synopsis

create-sc-leds-and-button-pcie-comp ["name"]

Description

This command creates a non-instantiated component of the class sc_leds_and_button_pcie_comp.

The class description for the sc_leds_and_button_pcie_comp class: PCIe card with a set of LEDs and buttons on its panel. Used for PCIe-based modeling tutorial, and as an example of system panel usage

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

sc-leds-and-button-pcie-dev

new-chassis-qsp-x86

Synopsis

new-chassis-qsp-x86 ["name"]

Description

This command creates an instantiated component of the class chassis_qsp_x86.

The class description for the chassis_qsp_x86 class: Chassis for QSP x86 systems.

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

x58-ich10-comp

new-chassis-x58-ich10

Synopsis

new-chassis-x58-ich10 ["name"]

Description

This command creates an instantiated component of the class chassis_x58_ich10.

The class description for the chassis_x58_ich10 class: Chassis for Intel® X58-ICH10 systems.

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

x58-ich10-comp

new-leds-and-button-panel

Synopsis

new-leds-and-button-panel ["name"]

Description

This command creates an instantiated component of the class leds_and_button_panel.

The class description for the leds_and_button_panel class: The system panel to display the front end of the LEDs and button device.

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

sc-leds-and-button-pcie-dev

new-motherboard-x58-ich10

Synopsis

new-motherboard-x58-ich10 ["name"] [acpi] ["apic_bus_class"] ["bios"] [break_on_reboot] ["lan_bios"] ["mac_address"] ["rtc_time"] ["spi_flash"] [system_clock] ["system_clock_class"]

Description

This command creates an instantiated component of the class motherboard_x58_ich10.

The class description for the motherboard_x58_ich10 class: Motherboard with Intel® X58 Express Chipset (northbridge) and Intel® ICH10 (southbridge).

name is Optional

If not specified, the component will get a class-specific default name.

acpi is Optional

Use ACPI when True, default value is True.

apic_bus_class is Optional

APIC bus classname

bios is Optional

The x86 BIOS file to use.

break_on_reboot is Optional

If true, the simulation will stop when machine is rebooted.

lan_bios is Optional

The Expansion ROM BIOS file for the ICH10 LAN.

mac_address is Optional

MAC address

rtc_time is Optional

The date and time of the Real-Time clock. Please note that time-zone information is not supported and will be silently dropped when passed to the RTC object.

spi_flash is Optional

The ICH10 SPI flash file to use.

system_clock is Optional

If true, the motherboard will contain a clock separate from the processor, which will be used as queue for all devices. The class used for the clock is taken from system_clock_class.

system_clock_class is Optional

The class used for the system_clock.

Provided By

x58-ich10-comp

new-sample-core-timing-tool

Synopsis

new-sample-core-timing-tool ["name"] ([ providers ... ] | list of providers) [parent] [-connect-all] ["group"]

Description

Creates a new sample-core-timing tool which can be connected to x86 cores.

The optional name argument can be used to set a name of the created object. If no name is given, a default name sample_core_timing followed by a sequence number is generated (sample_core_timing0, sample_core_timing1,...).

The optional providers argument, supports connecting one or several providers directly. With the optional parent argument a hierarchical object can be specified and all providers below this object matching the provider requirements will be connected to the tool. The -connect-all flag can be given to add a connection to all supported providers in the configuration.

The optional argument group let a user specify a named instrumentation group to use for the connection. (See add-instrumentation-group for details on named groups.)

Provided By

sample-core-timing

new-sc-leds-and-button-pcie-comp

Synopsis

new-sc-leds-and-button-pcie-comp ["name"]

Description

This command creates an instantiated component of the class sc_leds_and_button_pcie_comp.

The class description for the sc_leds_and_button_pcie_comp class: PCIe card with a set of LEDs and buttons on its panel. Used for PCIe-based modeling tutorial, and as an example of system panel usage

name is Optional

If not specified, the component will get a class-specific default name.

Provided By

sc-leds-and-button-pcie-dev

trace-vmread

Synopsis

trace-vmread (field|-all|-list)
<x86>.trace-vmread (field|-all|-list)
<x86>.untrace-vmread (field|-all|-list)
untrace-vmread (field|-all|-list)

Description

Enables and disables tracing of Intel® Virtual Machine Control Structure (Intel ® VMCS) reads. When this is enabled, every time the specified VMCS field is read during simulation a message is printed. The message will name the VMCS field being read, and the value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable tracing of all VMCS fields.

Using the -list argument will print out the VMCS fields accesses currently being traced.

The non-namespace variant of this command traces VMCS field reads on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

break-vmread, trace-vmwrite

trace-vmwrite

Synopsis

trace-vmwrite (field|-all|-list)
<x86>.trace-vmwrite (field|-all|-list)
<x86>.untrace-vmwrite (field|-all|-list)
untrace-vmwrite (field|-all|-list)

Description

Enables and disables tracing of Intel® Virtual Machine Control Structure (Intel ® VMCS) updates. When this is enabled, every time the specified VMCS field is updated during simulation a message is printed. The message will name the VMCS field being read, and the new value. The new value will be printed even if it is identical to the previous value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable tracing of all VMCS fields.

Using the -list argument will print out the VMCS fields accesses currently being traced.

The non-namespace variant of this command traces VMCS field updates on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

break-vmwrite, trace-vmread

unbreak-vmread

Synopsis

unbreak-vmread (field|-all|-list)
<x86>.break-vmread (field|-all|-list)
<x86>.unbreak-vmread (field|-all|-list)
break-vmread (field|-all|-list)

Description

Enables and disables breaking simulation on Intel® Virtual Machine Control Structure (Intel ® VMCS) reads. When this is enabled, every time the specified VMCS field is read during simulation a message is printed. The message will name the VMCS field being read, and the value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable breaking simulation on all VMCS fields.

Using the -list argument will print out the VMCS fields accesses on which a breakpoint will trigger.

The non-namespace variant of this command breaks the simulation on VMCS field reads on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

trace-vmread, break-vmwrite

unbreak-vmwrite

Synopsis

unbreak-vmwrite (field|-all|-list)
<x86>.break-vmwrite (field|-all|-list)
<x86>.unbreak-vmwrite (field|-all|-list)
break-vmwrite (field|-all|-list)

Description

Enables and disables breaking simulation on Intel® Virtual Machine Control Structure (Intel ® VMCS) updates. When this is enabled, every time the specified VMCS field is updated during simulation a message is printed. The message will name the VMCS field being read, and the new value. The new value will be printed even if it is identical to the previous value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable breaking simulation on all VMCS fields.

Using the -list argument will print out the VMCS fields accesses on which a breakpoint will trigger.

The non-namespace variant of this command breaks the simulation on VMCS field updates on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

trace-vmwrite, trace-vmread

untrace-vmread

Synopsis

untrace-vmread (field|-all|-list)
<x86>.trace-vmread (field|-all|-list)
<x86>.untrace-vmread (field|-all|-list)
trace-vmread (field|-all|-list)

Description

Enables and disables tracing of Intel® Virtual Machine Control Structure (Intel ® VMCS) reads. When this is enabled, every time the specified VMCS field is read during simulation a message is printed. The message will name the VMCS field being read, and the value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable tracing of all VMCS fields.

Using the -list argument will print out the VMCS fields accesses currently being traced.

The non-namespace variant of this command traces VMCS field reads on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

break-vmread, trace-vmwrite

untrace-vmwrite

Synopsis

untrace-vmwrite (field|-all|-list)
<x86>.trace-vmwrite (field|-all|-list)
<x86>.untrace-vmwrite (field|-all|-list)
trace-vmwrite (field|-all|-list)

Description

Enables and disables tracing of Intel® Virtual Machine Control Structure (Intel ® VMCS) updates. When this is enabled, every time the specified VMCS field is updated during simulation a message is printed. The message will name the VMCS field being read, and the new value. The new value will be printed even if it is identical to the previous value.

The field parameter specifies which VMCS field should be traced. The available VMCS fields depend on the simulated target.

Instead of a VMCS field number, the -all flag may be given. This will enable or disable tracing of all VMCS fields.

Using the -list argument will print out the VMCS fields accesses currently being traced.

The non-namespace variant of this command traces VMCS field updates on all processors that support the specified VMCS field. The namespace variant affects only the selected processor.

Provided By

x86-intel64

See Also

break-vmwrite, trace-vmread