boolean.
A20 will be always lowered if this flag is set.string.
Get string describing the specified access type (x86_access_type_t).boolean.
If this attribute is set to TRUE, which is the default, then VMP is allowed to modify the initial CPU state slightly in order to work around a BIOS problem causing hard host crashes. The workaround consist of using a 32-bit TSS instead of a 16-bit TSS after CPU reset. If this attribute is set to FALSE, then VMP will be disabled whenever a 16-bit TSS is loaded.[[o,i]*].
((address profiler, view)*) Address profiler views selected for this processor. Affects only the display of profiling information, and has nothing to do with collecting it.
This attribute should contain a list of lists: one list for each address profiler view you want to select (in the order they are to appear), each containing first the address profiler object, then the index of the desired view.
boolean.
Enables automatic detection of loops which can be hypersimulated.[[iis]*].
{ffwd_steps, addr, precond} Information on automatically found hypersim loops.integer.
INIT will be blocked if this flag is set.integer.
NMI will be blocked if this flag is set.integer.
SMI will be blocked if this flag is set.boolean.
If TRUE, the model will stop execution if there is a triple fault. Set to FALSE to not stop on triple fault.object or nil.
Object implementing the x86_cache_flush interface.integer.
Value returned in EAX for CPUID when input EAX == 2.integer.
Value returned in EBX for CPUID when input EAX == 2.integer.
Value returned in ECX for CPUID when input EAX == 2.integer.
Value returned in EDX for CPUID when input EAX == 2.integer.
Size of CLFLUSH as reported by CPUID.integer.
Number of bits for APIC ID shift at the core level in CPUID. The shift count at the thread level will be added to calculate the second 0xB sub-leaf shift count. If left at the default value of 0, a count just large enough to represent the cores in the package.integer.
Extended family for CPUID.integer.
Level 2 cache information returned by CPUID function 8000.0006.integer.
Level 2 cache information returned by CPUID function 8000.0006.integer.
Level 2 cache information returned by CPUID function 8000.0006.integer.
Level 2 cache information returned by CPUID function 8000.0006.boolean.
LAHF/SAHF support in 64-bit mode. Reported through CPUID function 80000001 in ECX bit 0.[o*].
List of objects implementing the x86_cpuid interface. These objects are called in the order of registration after the magic instruction handler but before internal CPUID implementationinteger.
Count of logical processors for CPUID. Setting this to non-zero will enable the HTT feature bit (bit 28).integer.
Support for MONITOR. Reported through CPUID function 1 ECX bit 3.integer.
Largest monitor granularity. This is reported through CPUID, but not used in the implementation.integer.
Smallest monitor granularity. This is the size used in the monitor implementation.boolean.
Support for MWAIT break on interrupts even if disabled.integer.
Physical local APIC ID for CPUID.integer.
Support for SSE3. Reported through CPUID function 1 ECX bit 0.integer.
Support for SSE4.1. Reported through CPUID function 1 ECX bit 19.integer.
Support for SSSE3. Reported through CPUID function 1 ECX bit 9.integer.
Number of bits for APIC ID shift at the thread level in CPUID. If left at the default value of 0, a count just large enough to represent the threads in the core will be used.integer.
VMX feature as reported through CPUID function 1 ECX bit 5.integer.
Externally implemented cr4 bits.[i{11}].
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.[o*].
List of all devices to be notified on C-state change. Must implement the x86_cstate_notification interface.object or nil.
Current context relating to addresses before segmentation.integer.
VMX mode current VMCS pointer.integer.
Time measured in cycles from machine start.boolean.
If this attribute is set to TRUE (FALSE is the default), then the 10b length encoding in DR7 is taken to mean 8 bytes. If it is false, then 10b means 8 bytes in long mode, but only one byte in legacy mode.integer.
Set to non-zero if you want debug breakpoints that are not enabled either through DR7.L nor DR7.G to still set the B bits in DR6.boolean.
Set to TRUE to prevent this object from being scheduled by the cell.[i{11}].
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.boolean.
If TRUE, the effective memory type field of memory transactions will always be calculated for all non-inquiry accesses. If FALSE, the effective memory type field may be left as X86_None.boolean.
TRUE if the processor is enabled. If FALSE, it will see time (cycles) pass but not execute steps.[i{11}].
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.[[o|n,s,i]*].
((object, description, time)*). All events in queue with a human-readable description. The attribute is indexed by queue (Sim_Queue_Step/Time).string or nil.
Description of current exception. Only valid when read from the Core_Exception hap. The value can be Nil in which case the exception number, source, and optional error code can be used to gain an understanding of why the exception triggered.integer.
Error code for the current exception. Only valid when read from the Core_Exception hap. This attribute is undefined for exceptions that do not have an error code.integer.
A bit indicating if the current exception is external.boolean.
If this attribute is set to TRUE, far call and jmp instructions will have a 64-bit offset when the operand size is 64-bits. If FALSE, then the offset will be 32-bits with both 32-bit and 64-bit operand size.object or nil.
Object to which the FERR pin (used for external x87 exception emulation) is connected.boolean.
Fopcode compatibility sub-mode.integer.
FPU instruction pointer offset.integer.
FPU instruction pointer selector.integer.
FPU operand pointer offset.integer.
FPU operand pointer selector.[[i{11}]{8}].
((empty, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9){8}). X86 floating point registers. The 8 80-bits registers is stored as a list of 11 bytes. The first byte tells if the register is empty (1) or not (0). The other bytes contain the register value with the lowest (least significant) bits in b0 and the highest (most significant bits in b9.float.
Maximum allowed value for the number of instructions executed per virtual second, expressed as a fraction of the current CPU frequency.float.
Minimum allowed value for the number of instructions executed per virtual second, expressed as a fraction of the current CPU frequency.float.
Freerun speed. A value of 1.0 means realtime.float or integer.
Processor clock frequency in MHz.[ii], [os], or object.
Processor clock frequency in Hz, as a rational number [numerator, denominator], or as a frequency provider implementing the frequency. The legacy simple_dispatcher is also supported.[i{11}].
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.[i{11}].
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.integer.
Actual Performance Frequency Clock Countinteger.
Processor Hard Power-On Configurationinteger.
Control Features in Intel64 processorinteger.
Fixed-Function Performance Counter Register 0integer.
Fixed-Function Performance Counter Register 1integer.
Fixed-Function Performance Counter Register 2integer.
Fixed-Function-Counter Control Registerinteger.
Swap Target of BASE Address of GSinteger.
IA-32e Mode System Call Target Addressinteger.
Enable Misc. Processor Featuresinteger.
Monitor/Mwait Address Range Determinationinteger.
Maximum Performance Frequency Clock Countinteger.
Global Performance Counter Controlinteger.
Global Performance Counter Statusinteger.
Performance Event Select Register 0integer.
Performance Event Select Register 1integer.
Reporting Register of Basic VMX Capabilitiesinteger.
Capability Reporting Register of CR0 Bits Fixed to 0integer.
Capability Reporting Register of CR0 Bits Fixed to 1integer.
Capability Reporting Register of CR4 Bits Fixed to 0integer.
Capability Reporting Register of CR4 Bits Fixed to 1integer.
Capability Reporting Register of VM-entry Controlsinteger.
Capability Reporting Register of VM-exit Controlsinteger.
Reporting Register of Miscellaneous VMX Capabilitiesinteger.
Capability Reporting Register of Pin-based VM-execution Controlsinteger.
Capability Reporting Register of Primary Processor-based VM-execution Controlsinteger.
Capability Reporting Register of VMCS Field Enumerationboolean.
If TRUE, the model will keep trying to cache memory through direct memory even if it fails.integer.
Set iff the processor is in system management mode.boolean.
Setting this attribute to true enables the use of virtual machine monitor acceleration. The attribute will flag it as an illegal value if the virtual machine monitor kernel module could not be found, or if there was an error opening a connection to it (the attribute reads back as false in those cases). Acceleration will not be used unless the use_vm_monitor attribute is also set to true.boolean.
TRUE if the processor is currently stalling by request of a timing-model.boolean.
If this attribute is set to TRUE (FALSE is the default), then the LDT segment type will not be considered valid for the LAR instruction while operating in long mode.[iiii].
Information about last IO instruction (pc, lin_addr, iinfo, step_count).[i{11}].
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.boolean.
If TRUE, the load far pointer instructions are extended to 64-bit when executed with a 64-bit operand size. The default is FALSE, which treats 64-bit and 32-bit operand size the same.string.
MP protocol. One of {'msi', 'ww', 'wwp'}integer.
Multicore Accelerator mode used by processor. One of Sim_Concurrency_Mode_Serialized (1), Sim_Concurrency_Mode_Serialized_Memory (2), or Sim_Concurrency_Mode_Full (4)integer.
The minimum size (in bytes) of a cache line that can be represented by Simics (when connecting a cache memhier).[bbi].
(armed, fired, address). Information about MONITOR. The MONITOR is armed if the first element in the list is true. The last element in the list contains the monitored physical address, and the second element indicates if the monitor has fired which means that the CPU should wake up.boolean.
If TRUE, movs to or from control and debug registers will default to 32-bits in 64-bit mode. If FALSE (which is the default value), such moves will be fixed at 64-bits.integer.
GBUSQ Event Control/Counter Registerinteger.
GBUSQ Event Control/Counter Registerinteger.
GSNPQ Event Control/Counter Registerinteger.
GSNPQ Event Control/Counter Registerinteger.
FSB Event Control/Counter Registerinteger.
FSB Event Control/Counter Registerinteger.
FSB Event Control/Counter Registerinteger.
FSB Event Control/Counter Registerinteger.
L3/FSB Common Control Registerinteger.
Last Branch Record 0 From IPinteger.
Last Branch Record 0 To IPinteger.
Last Branch Record 1 From IPinteger.
Last Branch Record 1 To IPinteger.
Last Branch Record 2 From IPinteger.
Last Branch Record 2 To IPinteger.
Last Branch Record 3 From IPinteger.
Last Branch Record 3 To IPinteger.
Last Branch Record Stack TOSinteger.
Last Exception Record From Linear IPinteger.
Last Exception Record To Linear IPboolean.
Multicore Accelerator enabled for processor.integer.
Extensions passed to the MWAIT instruction through ECX.integer.
Hints passed to the MWAIT instruction through EAX.boolean.
Determines how near branches are handled in 64-bit mode. If the attribute is TRUE, then the operand size is fixed at 64-bits, while the default value of FALSE allows an override to 16 bits.boolean.
If true, the processor is disabled by explicit user action and will not execute instructions until re-enabled by user. No architectural transitions, such as resets, will re-enable it on their own.boolean.
If TRUE, a load of a NULL selector to a segment register will clear the base and limit values.boolean.
If TRUE, each un-interrupted run of a repeated string instruction (CMPS, LODS, MOVS, SCAS, STOS) will be counted as a single step as compared to each iteration being a step in the default model. Due to how instruction counting works in the hardware performance counters, this attribute must be set to TRUE for VMP to work. Setting this attribute to FALSE will disable VMP.[i|[ii]|[iii]*].
((address, length, hits)*).Core_Address_Not_Mapped hap.object or nil.
The first Simics processor contained in the same multicore package. Used for shared MSR:s. Needs to point to a processor of the same class.integer.
Stall cycles for the PAUSE instruction. This additional stall is there to allow execution of spin-locks to consume more virtual time per iteration, leading to faster simulation performance. The default for VMP is to stall for 10 micro-seconds.integer.
A debug exception is pending. Additional information about the exception is stored in pending_debug_exception_dr6.integer.
Valid if pending_debug_exception is non-zero. Attribute has the same format as the DR6 register.boolean.
If this attribute is TRUE, then an exception or interrupt is pending and will be delivered before the next instruction.integer.
Error code to be delivered on the next pending exception if pending_exception_error_code_valid is set.boolean.
If this attribute is TRUE, then the pending exception has an error code.integer.
Length of pending trap instruction.boolean.
If this attribute is TRUE, then the resume flag bit will be set in the pushed image of the flag register.integer.
Type of pending exception. integer.
Pending interrupt or exception vector. Only valid if pending_exception is set.integer.
If 1, a startup IPI is pending.integer.
The address to start on if there is a pending startup IPI.object.
Physical memory space. Must implement memory-space, breakpoint and breakpoint_query interfaces.integer.
Stall cycles for port-mapped I/O. This additional stall is there to allow I/O poll loops to consume more virtual time per iteration, leading to faster simulation performance. The default for VMP is to stall for 10 micro-seconds.object.
I/O space of the cpu targeted by the IN, INS, OUT, and OUTS instructions. Must implement either the port interface (typically an instance of the port-space class), or the lookup interface (typically an instance of the memory-space class).integer.
Simics internal number for an instance of the 'processor_info' interface. Each instance must have a unique number. This attribute can only be set as part of an initial configuration.integer.
Stall cycles for the RDTSC and RDTSCP instructions. This additional stall is there to allow time expiration loops to consume more virtual time per iteration, leading to faster simulation performance. The default for VMP is to stall for 10 micro-seconds.boolean.
If this attribute is set to TRUE (which is the default), then segment register push instructions will pad the push with zero bytes up to the width of the push. If false, then that memory will be kept untouched.object or nil.
Points to the object representing the memory space shared between threads/cores. This is used to set up the monitoring to emulate MONITOR/MWAIT. If this is set to Nil, then MONITOR/MWAIT will time-out at the end of each time-quantum which is likely to result in non-optimal performance especially when the quantum is rather short.integer.
The simulation mechanism used for the processor. One of the values of the simulation_mode_t enum.boolean.
If TRUE, no canonical check is performed on the logical address during address translation. A canonical check is always performed on the linear address, regardless of the setting of this attribute. The default value is FALSE, performing canonical checks on both the logical and linear addresses.integer.
Counts the number of occurrences of the SMM.[os], object, or nil.
Object implementing the x86_smm interface.[o*].
List of all devices to be notified on transitions in or out of system management mode (SMM). Must implement the x86_smm_notification interface.boolean.
If this attribute is set to TRUE (FALSE is the default), then the stack pointer will be masked to 32-bits after the 16-byte alignment when an exception is taken from a mode other than 64-bit mode while operating in long mode.[i{11}].
Segment register. All fields are stored in a list of integers as follows: (selector, b, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.integer.
The number of cycles the processor will stall[iii].
If is_stalling is set, this contains information about the current memory operation.string.
"constant" indicates a constant finite step/cycle factor; "infinite" means that steps are run without advancing time.[[o|n,s,a,s,i]*].
((object, evclass, value, slot, step)*). Pending step queue events.integer.
Number steps executed since machine start.[o*].
List of objects that provides telemetry for this coreinteger.
If non-zero, interrupts are temporarily disabled even though EFLAGS.IF may be set.[[o|n,s,a,s|n,i]*].
((object, evclass, value, slot, cycle)*). Pending time queue events.[i{11}].
X86 segment register. All fields are stored in a list of integers as follows: (selector, d, dpl, g, p, s, type, base, limit, valid, l) The limit field always specifies the limit in bytes.integer.
Rate at which TSC (if TSC invariant feature supported) and IA32_MPERF MSR are incremented in cycles/second.integer or nil.
Can be either: None - no microcode update has happened since #RESET or an integer - microcode signature after the update.boolean.
Advance the step counter as well as the cycle counter when the CPU is idle. Defaults to FALSE.object or nil.
VMP-mode state-assertion object.integer.
Do not enter VMP if fewer steps has been executed since last time autohyper triggered (since the execution is likely handled by autohyper again). Default 30 steps.integer.
Execution with VMP will be prevented if this attribute is non-zero. This attribute should normally be modified using the x86_vmp_control interface.integer.
If set to non-zero, the VM-monitor will silently break execution as soon as possible after the specified step without impacting the normal execution flow.boolean.
This attribute should be set to TRUE if the machine configuration is VMP compatible.boolean.
Set if the host cpu might be affected by a hardware bug.boolean.
Internal. Used to test state migration between host cpus.integer.
If 1, the VMP kernel module will collect VMX traces. If 2, logging will occur to the console or to a file.string or nil.
Reason for using turbo instead of VM acceleration.boolean.
Dump VM-monitor trace information (only collected if vm_debug_trace is set).boolean.
If TRUE, host cpus support the virtual machine extensions (VMX).dictionary or nil.
Internal. Information about VMXMON.[[i*][i*][i*]].
Internal, used for performance evaluation.boolean.
Set if the physical address space may be shared with the other CPU cores.[b+].
Wire process to a subset of available hardware threads.integer.
Threshold below which the monitor is not used.boolean.
If TRUE set, the VMP kernel module will use CR0.TF to stop execution after each instruction (for debugging purposes).string or nil.
File for storing VM-monitor traces; Used for debugging VMP.boolean.
Set if the physical address space sharing should be used when possible.boolean.
Returns TRUE if physical address space sharing is in use.[[ii]*].
The register content of the currently loaded Intel® Virtual Machine Control Structure (Intel® VMCS). Not valid if current_vmcs_ptr is not valid. Not all VMCS fields are necessarily present in this attribute since they are not kept in CPU registers. Remaining fields will be in the VMCS memory area.[[isiii]*].
Exports the implementation specific layout of the Intel® Virtual Machine Control Structure (Intel® VMCS) area. This information can be used to display the current VMCS status, as well as to track changes in the VMCS. Sublist format (index, name, size, offset, attr). A field is stored as a size byte integer at offset in the VMCS.integer.
VMX mode. 0: Not in VMX operation. 1: In VMX root operation. 2: In VMX non-root operation.integer or nil.
Pending VMX exit reason. See appendix A of the VMX specification for encoding. Nil if no VMX exit is pending.object or nil.
The device that requested the waiting interrupt. Only valid when waiting_interrupt is non-zero.integer.
If an interrupt is requested, but it cannot be immediately handled because interrupts are masked.[[ii]*].
((xmm_0_low, xmm_0_high), ..., (xmm_n_low, xmm_n_high)). Each list represents one xmm register. The high quad word (bits 64-127) is in xmmi_high and the low quad word (bits 0-63) is in xmmi_low.[[ii]*].
((ymmu0_low, ymm0_high), ..., (ymmu15_low, ymmu15_high)). Each list represents the two upper quad words of an ymm register. register. The high quad word (bits 192-255) is in ymmi_high and the low quad word (bits 128-191) is in ymmi_low.
string.
Implemented architecture (x86-64)integer.
Number of physical address bits.
| aprof-views | manipulate list of selected address profiling views |
| break-processor-reset | break on processor reset |
| break-segreg | break on control register updates |
| info | print information about the object |
| memory-configuration | print memory configuration |
| msrs | print MSRs |
| pregs-fpu | print the x87 registers |
| pregs-sse | print the sse registers |
| print-acpi-tables | print ACPI tables |
| print-gdt | print GDT |
| print-idt | print IDT |
| print-mp-tables | print MP tables |
| print-tss | print TSS |
| print-vmcs | print VMCS |
| print-vmx-cap | print VMX capabilities of CPU |
| status | print status of the object |
| tablewalk | address translation tablewalk |
| trace-segreg | trace segment register updates |
| unbreak-processor-reset | stop breaking on processor reset |
| unbreak-segreg | break on control register updates |
| untrace-segreg | trace segment register updates |
| wait-for-processor-reset | wait for a processor reset |