ich10_sata_f2 ich10_smbus
Quick-Start Platform x86 Reference Manual  /  4 Classes  / 

ich10_sata_f5

Description
SATA controller function 5 in IntelĀ® ICH10.
Interfaces Implemented
bus_master_ide, conf_object, io_memory, log_object, pci_device
Port Objects
bank.bm (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view) : bus master IDE I/O registers
bank.pci_config (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.sata (bank_instrumentation_subscribe, instrumentation_order, int_register, register_view) : serial ATA registers
bank.sidp (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view) : serial ATA index/data pair registers
Port Interfaces
core_dev_access_count (probe) : Port for generic device access count
Provided By
ICH10

Attributes

chipset_config

Required attribute; read/write access; type: [os] or object. Chipset configuration registers

Required interfaces: int_register.

config_registers

Pseudo attribute; read-only access; type: [i*]. The PCI configuration registers, each 32 bits in size.

expansion_rom_size

Optional attribute; read/write access; type: integer. The size of the expansion ROM mapping.

ide

Optional attribute; read/write access; type: [o|[os]|n{0:2}]. Connections to two IDE controllers

Required interfaces: ide_dma_v2.

pci_bus

Required attribute; read/write access; type: [os] or object. The PCI bus this device is connected to, implementing the pci-bus interface.

Required interfaces: io_memory, pci_bus.

bank.pci_config.bist

Optional attribute; read/write access; type: integer. Build-in Self Test

bank.pci_config.cache_line_size

Optional attribute; read/write access; type: integer. CacheLine Size

bank.pci_config.capabilities_ptr

Pseudo attribute; read/write access; type: integer. Capabilities Pointer

bank.pci_config.cardbus_cis_ptr

Optional attribute; read/write access; type: integer. Cardbus CIS Pointer

bank.pci_config.class_code

Optional attribute; read/write access; type: integer. Class Code

bank.pci_config.command

Optional attribute; read/write access; type: integer. Command Register

bank.pci_config.device_id

Optional attribute; read/write access; type: integer. Device ID

bank.pci_config.header_type

Optional attribute; read/write access; type: integer. Header Type

bank.pci_config.interrupt_line

Optional attribute; read/write access; type: integer. Interrupt Line

bank.pci_config.interrupt_pin

Pseudo attribute; read/write access; type: integer. Interrupt Pin

bank.pci_config.interrupts

Optional attribute; read/write access; type: integer. Raised _internal_ interrupts

bank.pci_config.latency_timer

Pseudo attribute; read/write access; type: integer. Latency Timer

bank.pci_config.max_lat

Optional attribute; read/write access; type: integer. MAX_LAT

bank.pci_config.min_gnt

Optional attribute; read/write access; type: integer. MIN_GNT

bank.pci_config.msi_address

Optional attribute; read/write access; type: integer. Message Address

bank.pci_config.msi_capability_header

Optional attribute; read/write access; type: integer. Capability Header

bank.pci_config.msi_control

Optional attribute; read/write access; type: integer. Message Control

bank.pci_config.msi_data

Optional attribute; read/write access; type: integer. Message Data

bank.pci_config.revision_id

Optional attribute; read/write access; type: integer. Revision ID

bank.pci_config.status

Optional attribute; read/write access; type: integer. Status Register

bank.pci_config.subsystem_id

Optional attribute; read/write access; type: integer. Subsystem ID

bank.pci_config.subsystem_vendor_id

Optional attribute; read/write access; type: integer. Subsystem Vendor ID

bank.pci_config.vendor_id

Optional attribute; read/write access; type: integer. Vendor ID

Command List

Commands
infoprint information about the object
print-pci-config-regsprint PCI configuration registers
statusprint status of the object

ich10_sata_f2 ich10_smbus