ich10_lpc

Description

LPC bridge contains interrupt controllers, timers, RTC, Serial ports and Firmware hub for Intel® ICH10.

Interfaces Implemented

bridge, conf_object, hpet_msi, io_memory, log_object, pci_device, pci_interrupt, serial_interrupt_master

Port Objects

bank.acpi_io_regs (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.apm_io_regs (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.cs_conf (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.fixed_io (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.gpio_conf (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.pci_config (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
port.HRESET (signal)
port.SRESET (signal)
port.com1_in (signal)
port.com2_in (signal)
port.com3_in (signal)
port.com4_in (signal)
port.pirq (simple_interrupt) : port for PIRQ input
port.pirqe (signal) : port for PIRQE
port.pirqf (signal) : port for PIRQF
port.pirqg (signal) : port for PIRQG
port.pirqh (signal) : port for PIRQH

Port Interfaces

core_dev_access_count (probe) : Port for generic device access count

Provided By

ICH10

Attributes

SERIRQ_slave

Optional attribute; read/write access; type: [os], object, or nil. connects to slave device of serial interrupt transfer cycles

Required interfaces: serial_interrupt_slave.

coma_level

Required attribute; read/write access; type: integer. Interrupt Level of COM A

coma_pirq

Optional attribute; read/write access; type: [os], object, or nil. Connection to interrupt controller for COMB

comb_level

Required attribute; read/write access; type: integer. Interrupt Level of COM B

comb_pirq

Optional attribute; read/write access; type: [os], object, or nil. Connection to interrupt controller for COMB

config_registers

Pseudo attribute; read-only access; type: [i*]. The PCI configuration registers, each 32 bits in size.

cpus

Required attribute; read/write access; type: [o*]. CPUs receiving direct pin connections for NMI and SMI

expansion_rom_size

Optional attribute; read/write access; type: integer. The size of the expansion ROM mapping.

flash

Required attribute; read/write access; type: [os] or object. Connection to the SPI interface in the ICH

Required interfaces: io_memory.

fwh_device

Optional attribute; read/write access; type: [[oo|no]|n{12}]. Devices connected to the Firmware Hub. Each device is either [object, target, image] (as returned by flash_create_memory_anon) or Nil. The image object must implement the image interface. See memory_space.map attribute for requirements on object and target

hpet

Optional attribute; read/write access; type: [os], object, or nil. The High Precision Event Timer mapped through the hptc register

Required interfaces: io_memory.

ich10_corporate

Optional attribute; read/write access; type: boolean. ICH10 Corporate family chipset, true for ICH10D or ICH10DO

ioapic

Required attribute; read/write access; type: [os] or object. IOAPIC receiving PCI interrupt

Required interfaces: ioapic.

irq_dev

Optional attribute; read/write access; type: [os], object, or nil. Connect to 8259 which is the destination object of PIRQs routing

Required interfaces: simple_interrupt.

irq_level

Optional attribute; read/write access; type: [i{8}]. Raise count for PIRQ[A-H]

lpc_io

Optional attribute; read/write access; type: [os], object, or nil. IO space of LPC bus

Required interfaces: memory_space.

lpc_memory

Optional attribute; read/write access; type: [os], object, or nil. Memory space of LPC bus

Required interfaces: memory_space.

nmi_pin

Optional attribute; read/write access; type: integer. SMI pin status

pci_bus

Required attribute; read/write access; type: [os] or object. The PCI bus this device is connected to, implementing the pci-bus interface.

Required interfaces: io_memory, pci_bus.

bank.pci_config.bist

Optional attribute; read/write access; type: integer. Build-in Self Test

bank.pci_config.cache_line_size

Optional attribute; read/write access; type: integer. CacheLine Size

bank.pci_config.capabilities_ptr

Pseudo attribute; read/write access; type: integer. Capabilities Pointer

bank.pci_config.cardbus_cis_ptr

Optional attribute; read/write access; type: integer. Cardbus CIS Pointer

bank.pci_config.class_code

Optional attribute; read/write access; type: integer. Class Code

bank.pci_config.command

Optional attribute; read/write access; type: integer. Command Register

bank.pci_config.device_id

Optional attribute; read/write access; type: integer. Device ID

bank.pci_config.header_type

Optional attribute; read/write access; type: integer. Header Type

bank.pci_config.interrupt_line

Optional attribute; read/write access; type: integer. Interrupt Line

bank.pci_config.interrupt_pin

Optional attribute; read/write access; type: integer. Interrupt Pin

bank.pci_config.interrupts

Optional attribute; read/write access; type: integer. Raised _internal_ interrupts

bank.pci_config.latency_timer

Optional attribute; read/write access; type: integer. Latency Timer

bank.pci_config.max_lat

Optional attribute; read/write access; type: integer. MAX_LAT

bank.pci_config.min_gnt

Optional attribute; read/write access; type: integer. MIN_GNT

bank.pci_config.revision_id

Optional attribute; read/write access; type: integer. Revision ID

bank.pci_config.status

Optional attribute; read/write access; type: integer. Status Register

bank.pci_config.subsystem_id

Optional attribute; read/write access; type: integer. Subsystem ID

bank.pci_config.subsystem_vendor_id

Optional attribute; read/write access; type: integer. Subsystem Vendor ID

bank.pci_config.vendor_id

Optional attribute; read/write access; type: integer. Vendor ID

reset_target

Optional attribute; read/write access; type: [os], object, or nil. Signal triggered via write to RST_CNT, should reset the system.

Required interfaces: signal.

sci_pin

Optional attribute; read/write access; type: integer. SCI pin status

serial_port

Optional attribute; read/write access; type: [o|[os]|n{0:4}]. Connections to registers bank of NS16550 object

smi_pin

Optional attribute; read/write access; type: integer. SMI pin status

Command List

Commands

info	print information about the object
print-pci-config-regs	print PCI configuration registers
status	print status of the object