ich10_hpe_timer

Description

High precision event timer in Intel® ICH10

Interfaces Implemented

conf_object, io_memory, log_object, simple_interrupt

Port Objects

bank.regs (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
port.HRESET (signal)
port.SRESET (signal)

Port Interfaces

core_dev_access_count (probe) : Port for generic device access count

Provided By

ICH10

Attributes

comp_write_slow_cycles

Optional attribute; read/write access; type: integer. Number of cycles the cpu should be stalled when the comparator register is written (performance optimization)

intc_8259

Optional attribute; read/write access; type: [os], object, or nil. Connection to Intel 8259A Programmable Interrupt Controller.

Required interfaces: simple_interrupt.

intc_apic

Optional attribute; read/write access; type: [os], object, or nil. Connection to APIC interrupt controller.

Required interfaces: ioapic.

lpc

Optional attribute; read/write access; type: [os], object, or nil. LPC bridge used to deliver FSB interrupts.If no LPC bridge is specified, FSB interrupts will be sent directlyon the connected memory space.

Required interfaces: hpet_msi.

memory_space

Optional attribute; read/write access; type: [os], object, or nil. Memory space used for FSB interrupt deliveryused if the LPC bridge is not used for FSB interrupt delivery.

Required interfaces: memory_space.

start_time

Optional attribute; read/write access; type: float. Latest start time of the main counter

Command List

Commands

info	print information about the object
status	print status of the object