ich10_bridge

Description: DMI (Direct Media Interface) to PCI unit in Intel® ICH10.
Interfaces Implemented: bridge, conf_object, io_memory, log_object, pci_bridge, pci_device, pci_express, pci_upstream, translate
Port Objects: bank.outbound_io1 (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.outbound_io2 (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.outbound_mem1 (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.outbound_mem2 (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.outbound_mem3 (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
bank.pci_config (bank_instrumentation_subscribe, instrumentation_order, int_register, io_memory, register_view)
port.pltrst (signal)
Port Interfaces: core_dev_access_count (probe) : Port for generic device access count
Provided By: ICH10

Attributes

config_registers: Pseudo attribute; read-only access; type: [i*]. The PCI configuration registers, each 32 bits in size.

expansion_rom_size: Optional attribute; read/write access; type: integer. The size of the expansion ROM mapping.

mapping_setup: Optional attribute; read/write access; type: [i{15}]. Attributes for the different bridge mappings: io-memory up/down, memory up/down, prefetchable memory down: (io_down.priority, io_down.align_size, io_down.endian, mem_down.priority, mem_down.align_size, mem_down.endian, pref_down.priority, pref_down.align_size, pref_down.endian, io_up.priority, io_up.align_size, io_up.endian, mem_up.priority, mem_up.align_size, mem_up.endian)

pci_bus: Required attribute; read/write access; type: [os] or object. The PCI bus this device is connected to, implementing the pci-bus interface.
Required interfaces: io_memory, pci_bus, pci_express.

bank.pci_config.bist: Optional attribute; read/write access; type: integer. Build-in Self Test

bank.pci_config.bridge_control: Optional attribute; read/write access; type: integer. Bridge Control

bank.pci_config.cache_line_size: Optional attribute; read/write access; type: integer. CacheLine Size

bank.pci_config.capabilities_ptr: Pseudo attribute; read/write access; type: integer. Capabilities Pointer

bank.pci_config.class_code: Optional attribute; read/write access; type: integer. Class Code

bank.pci_config.command: Optional attribute; read/write access; type: integer. Command Register

bank.pci_config.device_id: Optional attribute; read/write access; type: integer. Device ID

bank.pci_config.header_type: Optional attribute; read/write access; type: integer. Header Type

bank.pci_config.interrupt_line: Optional attribute; read/write access; type: integer. Interrupt Line

bank.pci_config.interrupt_pin: Optional attribute; read/write access; type: integer. Interrupt Pin

bank.pci_config.interrupts: Optional attribute; read/write access; type: integer. Raised _internal_ interrupts

bank.pci_config.io_base: Optional attribute; read/write access; type: integer. I/O Base

bank.pci_config.io_base_upper: Optional attribute; read/write access; type: integer. I/O Base Upper 16 Bits

bank.pci_config.io_limit: Optional attribute; read/write access; type: integer. I/O Limit

bank.pci_config.io_limit_upper: Optional attribute; read/write access; type: integer. I/O Limit Upper 16 Bits

bank.pci_config.irq_pin_count: Optional attribute; read/write access; type: [i{4}]. Forwarded interrupt count for bridges

bank.pci_config.latency_timer: Optional attribute; read/write access; type: integer. Latency Timer

bank.pci_config.memory_base: Optional attribute; read/write access; type: integer. Memory Base

bank.pci_config.memory_limit: Optional attribute; read/write access; type: integer. Memory Limit

bank.pci_config.prefetchable_base: Optional attribute; read/write access; type: integer. Prefetchable Memory Base

bank.pci_config.prefetchable_base_upper: Optional attribute; read/write access; type: integer. Prefetchable Memory Base Upper 32 Bits

bank.pci_config.prefetchable_limit: Optional attribute; read/write access; type: integer. Prefetchable Memory Limit

bank.pci_config.prefetchable_limit_upper: Optional attribute; read/write access; type: integer. Prefetchable Memory Limit Upper 32 Bits

bank.pci_config.primary_bus_number: Optional attribute; read/write access; type: integer. Primary Bus Number

bank.pci_config.revision_id: Optional attribute; read/write access; type: integer. Revision ID

bank.pci_config.secondary_bus_number: Optional attribute; read/write access; type: integer. Secondary Bus Number

bank.pci_config.secondary_latency_timer: Optional attribute; read/write access; type: integer. Secondary Latency Timer

bank.pci_config.secondary_status: Optional attribute; read/write access; type: integer. Secondary Status

bank.pci_config.status: Optional attribute; read/write access; type: integer. Status Register

bank.pci_config.subordinate_bus_number: Optional attribute; read/write access; type: integer. Subordinate Bus Number

bank.pci_config.vendor_id: Optional attribute; read/write access; type: integer. Vendor ID

secondary_bus: Required attribute; read/write access; type: [os] or object. Secondary bus
Required interfaces: io_memory, pci_bus, pci_downstream.

Commands

info	print information about the object
print-pci-config-regs	print PCI configuration registers
status	print status of the object