The following statistics are available in a simple_cache:
- Read accesses
Total number of read accesses
- Read misses
Total number of read accesses
- Write accesses
Total number of write accesses
- Write misses
Total number of write misses
- Write backs
Total number of write backes to this caches (from previous level)
- Write backs misses
Total number of write backes misses to this caches (from previous level)
- Request for write accesses
previous level wants to write to this line but missed and now request it for writing at this level
- Request for write misses
previous level wants to write to this line but missed and now request it for writing at this level but misses
- Prefetch accesses
Prefetches from either hardware prefetching or from instructions (software)
- Prefetch misses
Prefetches from either hardware prefetching or from instructions (software) that misses
- Request for write prefetch accesses
previous level wants to prefetch a write to this line but missed and now request it for write prefetching at this level
- Request for write prefetch misses
previous level wants to prefetch a write to this line but missed and now request it for write prefetching at this level, and misses
- Prefetches used
Prefetches that was later used for reading or writing, i.e., not wasted prefetches
- Prefetch instructions
Number of prefetch instructions directed to the cache
- Instruction fetch accesses
Total number of instruction fetches
- Instruction fetch misses
Total number of instruction fetches misses
- Evicted modified
Total number of evicted cache lines that was modified and needed to be written back to the next level
- Evicted total
Total number of evicted cache lines (including evicted modified)
- Evicted total
Total number of evicted cache lines (including evicted modified)
- Cache flush instructions
Number of cache flush instructions for flushing entire cache, inv and wbinvd
- Cache line flushs
Number of cache lins flush instructions (clflush)
- Uncachable reads
Total number of non-cacheable reads
- Uncachable writes
Total number of non-cacheable writes
Here is an example of the statistics using the print-statistics command:
simics> board.mb.cpu0.cache[0].l1d.print-statistics
Using the 'board.mb.cpu0.core[0][0]' processor for the Steps/Count column
┌─────┬───────────────────────────────────┬─────────┬─────┐
│Row #│ Counter │ Value │ % │
├─────┼───────────────────────────────────┼─────────┼─────┤
│ 1│read accesses │724945650│ │
│ 2│read misses │ 2678946│ 0.37│
│ 3│write accesses │555916819│ │
│ 4│write misses │ 12439648│ 2.24│
│ 5│prefetch accesses │ 8120411│ │
│ 6│prefetch misses │ 5158065│63.52│
│ 7│prefetched lines used │ 3533041│43.51│
│ 8│prefetch instructions │ 298374│ │
│ 9│evicted modified lines │ 13465148│66.41│
│ 10│evicted total lines │ 20275891│ │
│ 11│uncachable read accesses │ 56576127│ │
│ 12│uncachable write accesses │ 39916459│ │
└─────┴───────────────────────────────────┴─────────┴─────┘
Counts with a value of zero are not printed.