RISC-V CPU Release Notes

1 Introduction

This document identifies important information for the RISC-V CPU package for Simics 6. All users of this specific package should review this document carefully.

2 Changes Since Version 6.0.0

The following is a list of changes since the initial 6.0.0 release.

• 6.0.60 (build 6257)

  • CPU generic
    • Linux only: If the kernel supports Transparent Huge Pages (THP), the JIT code area now makes use of 2MB TLB mappings. This could slightly increase execution performance.
  • RISC-V Generic Package Changes
    • Update model to support Machine ISA 1.12.
      MRET and SRET clear mstatus.MPRV when leaving Machine mode
      CSR mconfigptr added
      CSR mseccfg and RV32-only CSR mseccfgh added. CSR menvcfg, henvcfg, senvcfg and RV32-only menvcfgh and henvcfgh added
      An additional 48 PMP registers are now supported.

• 6.0.59 (build 6247)

  • RISC-V Generic Package Changes
    • The locking of PMP entry was not correctly implemented (bug #SIMINT-1596).

• 6.0.58 (build 6235)

  • RISC-V Interrupt Controllers
    • Fixed a problem in the info command. The package now requires Simics-Base 6.0.170 or later.

• 6.0.57 (build 6233)

  • CPU generic
    • An issue with an internal cache was fixed. The fix considerably improves simulation performance in certain cases.

• 6.0.56 (build 6231)

  • RISC-V Generic Package Changes
    • The package now contains a file third-party-programs.txt with a list of third party software included in the package.

• 6.0.55 (build 6218)

  • Generic RISC-V CPU model Changes
    • Add new attributes to control processor core extensions. Misa extensions can be configured using extensions.A, extensions.C, extensions.D, extensions.F, extensions.I, extensions.M, extensions.S and extensions.U. The available attributes depend on what can be configured in each processor core class.

      Other extensions can be configured using the following attributes extensions.Zba, extensions.Zbb, extensions.Zbc and extensions.Zbs.

  • RISC-V Generic Package Changes
    • Changed default max MMU mode supported for the generic riscv-rv64 core to Sv39. Max supported mode can still be changed using the mmu_mode_support attribute.

• 6.0.54 (build 6215)

  • Generic RISC-V CPU model Changes
    • Bitmap extensions no longer use B-extension in the misa register. Use Zba, Zbb, Zbc and Zbs fields in isa_variants attribute to control available instructions.
    • Fix bug when accessing CSR register stvec old value was incorrectly taken from CSR register mtvec.

• 6.0.pre53 (build 6209)

  • RISC-V Interrupt Controllers
    • Added support for stalling the CPU when mtime is read. The number of cycles to stall can be set in the attribute mtime_read_cycles which defaults to 0.

• 6.0.pre52 (build 6205)

  • Generic RISC-V CPU model Changes
    • Lower bits of writes to csr stvec are now masked according to implemented interrupt features.
    • Accesses to user mode shadowed hardware performance counters are now checked against CSR mcounteren and scounteren if available.
    • The number of available ASID bits is now set to 0 by default. It is still possible to change through the ASIDLEN attribute.
    • A new attribute trap_on_rdtime has been added to control the behavior of pseudo instructions rdtime and rdtimeh.
  • RISC-V Generic Package Changes
    • Moved the Simple RISC-V target platform to its own package 2053.
  • RISC-V Interrupt Controllers
    • Added interrupt source list to PLIC info command. It is now simple to view the interrupt map of peripheral devices connected to the PLIC.

• 6.0.pre51 (build 6200)

  • Generic RISC-V CPU model Changes
    • Added CLOCK_DISABLE signal port (bug #HSD-18020152725).
  • RISC-V Interrupt Controllers
    • Added CLOCK_DISABLE signal ports to clint and plic (bug #HSD-18020152725).
    • Added HRESET signal port to plic.

• 6.0.pre50 (build 6190)

  • Generic RISC-V CPU model Changes
    • Add attribute mmu_mode_support to control MMU mode support.
    • Fixed autohyper issue resulting in ASSERTION ERROR. The problem only occurs on cores without ext-C, compressed instructions.

• 6.0.pre49 (build 6187)

  • RISC-V Generic Package Changes
    • Packages 2050 and 2052 has swapped number so that 2050 is generic RISC-V models and 2052 is SiFive models.

• 6.0.pre47 (build 6185)

  • RISC-V Generic Package Changes
    • New package with generic RISC-V cores riscv-rv64 and riscv-rv32.
  • RISC-V Interrupt Controllers
    • Removed sifive clic e2x from public distribution. It is now restricted to internal intel only.

• 6.0.pre46 (build 6181)

  • CPU generic
    • Temporarily rolled back minimum host processor requirements to Nehalem, since some systems need more time to migrate to match the official Haswell requirement (bug #HSD-18024604079).
  • Generic RISC-V CPU model Changes
    • Corrected some floating point operations involving NaNs (bug #HSD-22015869714).

• 6.0.pre45 (build 6180)

  • Generic RISC-V CPU model Changes
    • Support for Sv32 and supervisor mode for RV32 has been added.
    • The generic RISC-V CPU class riscv-rv32 now has support for supervisor mode and extension D.

• 6.0.pre44 (build 6179)

  • CPU generic
    • The instrumentation for System Management Mode (smm_instrumentation_subscribe interface) does not block VMP execution anymore, (bug #SIMICS-19625).

• 6.0.pre43 (build 6178)

  • Generic RISC-V CPU model Changes
    • Add support for Zbc and Zbs variants of the Bit-Manipulation ISA-extensions.
    • Add missing hint instructions in the RVC encoding space.

• 6.0.pre40 (build 6163)

  • Generic RISC-V CPU model Changes
    • Several issues with instrumentation are fixed. All of the instrumentation api is now available to use with RISC-V models.
    • Haps added for mode change, csr accesses and return from exception.

• 6.0.pre39 (build 6161)

  • Generic RISC-V CPU model Changes
    • Some information log messages has been moved to new levels. Illegal instructions is now on level 2 and IRQ level changes are now on level 3.
    • All RV64 core models now include all 32 event counters. The event counters are hardwired to zero.

• 6.0.pre38 (build 6160)

  • Generic RISC-V CPU model Changes
    • Magic instruction is added. SRAI zero, zero, imm will trigger Hap for magic instruction with imm as parameter.

• 6.0.pre37 (build 6152)

  • CPU generic
    • All CPUs have been updated to issue transactions to the memory space connected to the physical_memory attribute through the transaction interface, instead of sending memory transactions through the memory_space interface.
  • RISC-V Interrupt Controllers
    • Correctly mask access to enabled register in PLIC when the number of supported interrupts is not a multiple of 32.

• 6.0.pre36 (build 6150)

  • CPU generic
    • Simics now stops with an error, instead of a message, if the event queue overflows
  • Generic RISC-V CPU model Changes
    • Internal page caching is now ASID aware.

• 6.0.pre35 (build 6145)

  • Generic RISC-V CPU model Changes
    • Add support for Zba and Zbb variants of the Bit-Manipulation ISA-extensions. A new attribute isa_variants holds the supported variants for a core.

• 6.0.pre34 (build 6144)

  • CPU generic
    • Parallel JIT compilation: JIT blocks compiled, but later rejected for insertion, previously leaked a resource. This has now been fixed. If many blocks were rejected, the lack of resources caused a reduced amount of blocks could be compiled, and eventually no blocks where compiled at all (bug #HSD-14015758898).
  • Generic RISC-V CPU model Changes
    • Read only csrs mvendorid, marchid, mimpid and mhartid are no longer reset to zero when a core is reset (bug #HSD-18020627325).

• 6.0.pre33 (build 6143)

  • Generic RISC-V CPU model Changes
    • Rename exception for misaligned store/AMO access to Exc_Store_AMO_Address_Misaligned.
    • New MMU implemented with TLB. Added attribute ASIDLEN to control number of bits available for asid.

• 6.0.pre31 (build 6141)

  • CPU generic
    • Instrumentation: fixed an assertion error for processor models without JIT support. This previously happened when calling the instruction_query->logical_address() method (bug #HSD-1309492050).

• 6.0.pre30 (build 6133)

  • RISC-V Interrupt Controllers
    • Removed the obsolete internal attribute interrupts from the class riscv-plic which used to serve as backing storage for the attribute irq_dev.
    • Removed use of internal method _log_miss.

• 6.0.pre29 (build 6131)

  • Generic RISC-V CPU model Changes
    • Add two generic cores, riscv-rv32 that is a RV32IMAFC core with support for user mode, and riscv-rv64 that is a RV64GC core with support for user mode and supervisor mode. Both these cores support physical memory protection and local platform interrupts as an alternative to PLIC.
    • Add NIOS V/m core. It implements RV32IA together with local platform interrupts. The core class is called riscv-nios-v-m.

• 6.0.pre28 (build 6130)

  • Generic RISC-V CPU model Changes
    • Port interfaces has been redesigned as real port-objects. This affects MSIP, MTIP, MEIP, SEIP, HRESET, reset_vector, inject_halt_error and control_debug_mode. There are now objects for all of these ports. Ex: core_object.ports.MEIP.signal can now be found at core_object.port.MEIP.iface.signal. Signals accessed through clint, plic or clic are not affected by this change.

• 6.0.pre27 (build 6129)

  • CPU generic
    • Fixed a bug that prevented VMP to be reengaged after all instrumentation callbacks have been removed (bug #SIMICS-10259).
  • Generic RISC-V CPU model Changes
    • Outgoing signals has been added for halt state and debug state. Halt state and debug state are only supported as execution states. There is no error checking that can trigger halt state and there is no debug module simulation.

      To inject a halt error call the set method in the uint64_state interface on port inject_halt_error with the value one. In halt mode the halt_from_tile signal is raised. The core will stay in halt state until reset.

      Debug mode can be controlled through the uint64_state on port control_debug_mode. Call the set method with the value 1 to enter debug-mode and zero to exit debug-mode. During debug mode the core is disabled and the debug_from_tile signal is raised. The core will stay in Debug mode over a core reset (bug #HSD-18018543567).

    • Fix problem with checkpointing of MIP register when SEIP signal is raised (bug #SIMINT-1450).
    • Add attribute writable_misa to control which bits in the misa can be written to from instructions. This does not affect changes to the attribute misa from CLI and Python. Default for writable_misa is 0.
    • It is now possible to disable the compressed instructions extension (C). A new read-only attribute IALIGN holds the minimum alignment of instructions.
    • A new model targeting a generic RISC-V RV32EMA is added. Main difference is that it only has 16 general purpose registers.

• 6.0.pre26 (build 6120)

  • Generic RISC-V CPU model Changes
    • Virtual address instead of physical address is written to mtval with unhandled unaligned access exceptions (bug #SIMINT-1422).

• 6.0.pre25 (build 6117)

  • Generic RISC-V CPU model Changes
    • Exceptions are now raised for unhandled unaligned data accesses. A new attribute exception_for_unaligned_data_access has been added to control if the core handles unaligned accesses or not (bug #SIMINT-1422).

• 6.0.pre24 (build 6116)

  • Generic RISC-V CPU model Changes
    • Fix PMP NAPOT range calculation (bug #SIMINT-1423).

• 6.0.pre23 (build 6114)

  • RISC-V Interrupt Controllers
    • Fix segfault when writing bad values to claim register (bug #SIMICS-17663).

• 6.0.pre22 (build 6110)

  • Common
    • Simics no longer comes with documentation in PDF format.

• 6.0.pre21 (build 6105)

  • Generic RISC-V CPU model Changes
    • Added SiFive specific CSRs, bpm with CSR address 0x7c0 and csr_0x7c1 with CSR address 0x7c1. None of the features controlled by these CSR's are modeled. These CSRs are available for SiFive models e31, e34, s54, u54 and u74 (bug #HSD-18016853795).

• 6.0.pre20 (build 6103)

  • Generic RISC-V CPU model Changes
    • Fixed register description for CSR registers (bug #HSD-18016707847).

• 6.0.pre19 (build 6098)

  • CPU generic
    • Added support for obtaining the CPU frequency from an object implementing the frequency interface.

• 6.0.pre18 (build 6096)

  • Generic RISC-V CPU model Changes
    • Improved checkpoint stability.
    • Added support for HRESET signal.
    • Added SiFive specific instructions CEASE and PAUSE.
    • Added outgoing signals for WFI and CEASE. They can be setup using the attributes wfi_signal_target and cease_from_tile_signal_target.
    • Added attributes reset_config_clear_gprs, reset_config_clear_fprs and reset_config_reset_all_csrs to allow control over how muchof the core's state is cleared at reset. Interrupt state, PMP configuration and MMU setup are always reset to startup state at reset.

• 6.0.pre17 (build 6093)

  • Generic RISC-V CPU model Changes
    • Added support for SiFive E2x variant of clic.

• 6.0.pre16 (build 6092)

  • RISC-V Interrupt Controllers
    • Added class sifive-clic-e2x which models a SiFive* E2x Core-Local Interrupt Controller.
    • Fix bug in PLIC pseudo-attribute hart.

• 6.0.pre15 (build 6091)

  • Generic RISC-V CPU model Changes
    • Added floating point registers to int-register interface and describe_registers interface. Float variables are still not shown correctly on harts with the 64-bit floating point extension (bug #SIMINT-1367).

• 6.0.pre14 (build 6086)

  • Generic RISC-V CPU model Changes
    • Improved assignments of misa attribute.

• 6.0.pre13 (build 6084)

  • Generic RISC-V CPU model Changes
    • Fixed bug with masks used with updates to csr's mie and mip (bug #HSD-18014989371).

• 6.0.pre12 (build 6082)

  • Common
    • Documentation in HTML format has been added.

• 6.0.pre11 (build 6081)

  • Generic RISC-V CPU model Changes
    • Added some missing parts of the int_register and describe_registers (bug #SIMINT-1347).

• 6.0.pre10 (build 6080)

  • Generic RISC-V CPU model Changes
    • Fixed problem with accessing some of the supervisor SCR's that are filtered machine SCR.
    • Added way to customize core. Extensions can be disabled by writing a new value to misa. Number of PMP address registers can be set through number_of_pmp_address_registers. To remove PMP support write 0 to number_of_pmp_address_registers.
    • Corrected alignment of address used to flush specific 4K region with sfence.vma instruction (bug #SIMINT-1329).
    • Added support for state-assertion.
  • RISC-V Interrupt Controllers
    • Renamed classes riscv_plic to riscv-plic and riscv_clint to riscv-clint (aliases added for the old names).
    • Added attributes max_interrupt, max_priority and hart to the riscv-plic.

• 6.0.pre9 (build 6076)

  • Generic RISC-V CPU model Changes
    • Released inside Intel.

• 6.0.pre8 (build 6068)

  • CPU generic
    • Reduce the dynamic memory foot-print of automatic hypersim (even further) (bug #HSD-1507506841) and (bug #SIMICS-16237).

• 6.0.pre6 (build 6047)

  • RISC-V Interrupt Controllers
    • Initial release of CLINT and PLIC

• 6.0.pre5 (build 6043)

  • CPU generic
    • Correctly reduce the memory foot-print for automatic hypersim detection. The previous attempt was not working (bug #HSD-1507506841).
  • Common
    • Fixed a problem on Windows where the installer still asked for the Model Builder key (bug #SIMINT-1236).

• 6.0.pre4 (build 6037)

  • CPU generic
    • Made messages from the register-break command uniform with messages from other breakpoints (bug #SIMICS-15051).

• 6.0.pre3 (build 6032)

  • Common
    • Support for Python 2.7 has been removed. Simics now only embeds a Python 3 interpreter.

• 6.0.pre2 (build 6030)

  • Common
    • The separation of source code into separate packages has been removed. Source code is now included directly into each package.

• 6.0.pre1 (build 6028)

  • CPU generic
    • Avoid huge memory consumption when doing automatic hypersim detection for large complex blocks (bug #HSD-1507506841).
  • Common
    • The installers for Linux and macOS have been updated. Support for fallback mode of decryption keys has been removed.

• 6.0.pre0 (build 6025)

  • CPU generic
    • Fixed an unusual problem where the JIT-compilation engine was disabled when failing to allocate memory with low addresses (only noticed with Python3 and Windows host). Now low address-allocation is not done anymore (bug #HSD-2208230108).
    • Remove assertion error checks from (enable/disable)_connection_callbacks methods in the cpu_instrumentation_subscribe interface. This could happen if the user has not yet installed any callback for a connection. Typically the implementation of enable/disable in the connection_interface would call this methods. Now it it is unnecessary to check whether any callbacks has been installed before calling this method. This only affects instrumentation usage available in package 1022 (bug #HSD-1808121154).
    • A bug in <cpu>.unbreak-register command was fixed. Previously, the command failed to delete a breakpoint in some cases.
    • A new <cpu>.break-register command has been added, allowing the user to break both when general and control registers are updated. See the command for details. Note that this feature only exists for CPUs which supports the new CPU instrumentation interfaces. The command is added in simics-base rev 5.0.189. To use this new command, both simics-base and cpu packages need to be updated.
    • Fixed a rare instrumentation bug where instruction-after callbacks might be missed in JIT generated code (bug #SIMICS-12789).
    • Fixed a bug in measurement of how many instructions that was executed in JIT. Previously, exceptions triggered inside the JIT block, caused too few instructions to be accounted for. This lead to system-perfmeter presenting incorrect JIT% figures (bug #SIMICS-9280).
  • Generic RISC-V CPU model Changes
    • First release of the RISC-V CPU models.

3 Changes in version 6

4 Limitations

This section briefly describes the known limitations of the RISC-V CPU package. Please refer to section 5 for a more technical description.

For model oriented packages, additional limitations may be found in the model target guides.

5 Detailed List of Limitations

This section describes in detail the known limitations of the RISC-V CPU package. Please refer to section 4 for a more general description.

A register or field marked as Not implemented is present with read-write semantics but has no side effects on simulation. A register marked as Not implemented (design limitation) has the same semantics as a "Not implemented" register and there is no plan to extend the model with this functionality. A register with Lack of documentation has not been implemented because there is no available documentation describing its semantics.