Quick-Start Platform x86 Release Notes

1 Introduction

This document identifies important information for the Quick-Start Platform x86 package for Simics 6. All users of this specific package should review this document carefully.

2 Changes Since Version 6.0.0

The following is a list of changes since the initial 6.0.0 release.

3 Changes in version 6

4 Limitations

This section briefly describes the known limitations of the Quick-Start Platform x86 package. Please refer to section 5 for a more technical description.

For model oriented packages, additional limitations may be found in the model target guides.

ich10_lpc - model of Intel® ICH10 LPC bridge:

ich10_sata_f2 - model of Intel® ICH10 SATA controller: FIS-based Switching is not implemented. Port Multipliers are not implemented. Multiple MSI based messages are not implemented. Enclosure Management is not implemented. Command Completion Coalescing is not implemented. Device Sleep is not implemented.

ich10_smbus - model of Intel® ICH10 SMBus unit:

ich10_usb_uhci - model of Intel® ICH10 USB UHCI:

ich10_usb_ehci - model of Intel® ICH10 USB EHCI:

x58-core-f1-legacy - model of scratchpads and GPIO unit:

x58-core-f2-legacy - model of IOH control/status and RAS unit:

x58-core-f3-legacy - model of X58 throttling unit:

x58-qpi-port0-f0-legacy - model of QuickPath Interconnect port 0/0:

x58-qpi-port0-f1-legacy - model of QuickPath Interconnect port 0/1:

x58-qpi-port1-f0-legacy - model of QuickPath Interconnect port 1/0:

x58-qpi-port1-f1-legacy - model of QuickPath Interconnect port 1/1:

x58-pcie-port-legacy - model of X58 PCIe root port:

x58-remap-unit0-legacy - model of DMA/Interrupt remapping unit 0:

x58-remap-unit1-legacy - model of DMA/Interrupt remapping unit 1:

x58-qpi-ncr-f0-legacy - model of QuickPath Interconnect Non-Core Registers:

x58-qpi-sad-f1-legacy - model of QPI System Address Decoder Regs:

ich10_lan_v2 - model of Intel® ICH10 Gb Ethernet controller:

X58:

5 Detailed List of Limitations

This section describes in detail the known limitations of the Quick-Start Platform x86 package. Please refer to section 4 for a more general description.

A register or field marked as Not implemented is present with read-write semantics but has no side effects on simulation. A register marked as Not implemented (design limitation) has the same semantics as a "Not implemented" register and there is no plan to extend the model with this functionality. A register with Lack of documentation has not been implemented because there is no available documentation describing its semantics.



ich10_lpc - model of Intel® ICH10 LPC bridge:

The following banks have limitations:

The following registers have limitations:

ich10_sata_f2 - model of Intel® ICH10 SATA controller:

The following registers have limitations:

ich10_sata_f5 - model of Intel® ICH10 SATA:

The following registers have limitations:

ich10_smbus - model of Intel® ICH10 SMBus unit:

The following registers have limitations:

ich10_usb_ehci - model of Intel® ICH10 USB EHCI:

The following registers have limitations:

ich10_bridge - model of Intel® ICH10 DMI to PCI unit:

The following registers have limitations:

x58-ioxapic-legacy - model of X58 IOxAPIC unit:

The following registers have limitations:

x58-qpi-sad-f1-legacy - model of QPI System Address Decoder Regs:

The following registers have limitations:

ich10_lan_v2 - model of Intel® ICH10 Gb Ethernet controller:

The following registers have limitations: