Intel® Compiler for SystemC*

SystemC Compiler HLS
synthesizable SystemC to SystemVerilog RTL translation

Synthesizable SystemC SC_MODULE(dut) { sc_in<bool> clk; sc_in<bool> rst; SC_CTOR(dut) { SC_CTHREAD(proc, clk.pos()); async_reset_signal_is(rst,0); } void proc() {} }; SystemC Compiler Clang / LLVM 18 • SystemC 3.0.1 checks • elaboration • codegen SystemVerilog RTL module dut( input logic clk, input logic rst); always_ff @(posedge clk or negedge rst) begin end endmodule

Intel® Compiler for SystemC* is a High-Level Synthesis (HLS) tool which translates synthesizable SystemC into equivalent SystemVerilog RTL. The SystemC Compiler checks a SystemC design for common coding mistakes and generates human-readable SystemVerilog code which looks similar to the original SystemC.

DEVELOPMENT SPEED 10x FASTER ITERATION SystemC Templates OOP / Reusability SystemVerilog RTL Synthesized & Ready

Hardware engineering delivery speed and efficiency

The SystemC Compiler maximizes design and verification engineering productivity by leveraging the high-level abstraction and expressive power of the SystemC ecosystem.

Built on the Clang/LLVM frontend, the SystemC Compiler performs dynamic elaboration, enabling flexible design structures through module templates, constructor parameters, and end-of-elaboration callbacks. Code correctness analysis ensures that the generated SystemVerilog is fully equivalent to the SystemC source.

By applying only minimal transformations and delegating optimization to the underlying logic synthesis tool, the SystemC Compiler produces human-readable SystemVerilog that can be easily matched to the original SystemC code — simplifying power and timing analysis as well as ECO fixes.

Core IP Assembly Error-Free Structural Composition Verified 0 Faults sct_fifo Handshake Lock Memory Block SRAM / Register sct_pipe Retime Stage sct_target Ready Initiator

Reliable design with reusable components and assertions

Assembling hardware IP from pre-existing components minimizes design code size and significantly lowers error rates. Over the past 15 years, we have built the Single Source Library, a robust collection of reusable hardware primitives including channels, ports, buffers, and memory wrappers. We also provide custom sct_uint and sct_int data types to extend native, bit-accurate SystemC types. Additionally, the SystemC Compiler library includes high-utility functions optimized for both simulation and synthesis.

To simplify debugging and eliminate integration errors, the SystemC Assertion Library provides a comprehensive suite of immediate and temporal assertion macros. These macros support thread and method processes, collection validation, and module-level checks. For downstream verification, the SystemC Compiler automatically translates these checks into standard SystemVerilog Assertions (SVA).

AI

Intelligent Agent-Based Hardware Development Workflow

Automated hardware design using modern Large Language Models (LLMs) is a promising frontier with diverse applications. AI elevates the hardware coding process, allowing engineers to focus on high-level system problems and tasks while delegating low-level HDL implementation details to AI agents.

To support this workflow, the SystemC Compiler integrates synthesizable, SystemC-aware AI skills that enable accurate code generation and analysis. For instance, the AI Linter Agent analyzes SystemC code much like a traditional static analysis tool. It automatically detects and reports various errors, including functional flaws, inter-process synchronization bugs, improper type usage, arithmetic issues, potential overflows, and style violations.

SystemC Compiler Framework

SYSTEMC COMPILER PLATFORM Unified HLS Toolchain • Reusable Hardware Libraries • AI Skills & Verification Ecosystem SystemC Code Translation Clang / LLVM 18 Frontend • Synthesizable C++ subset parsing • AST processing & type validation Dynamic Elaboration Engine • Module templates & callbacks • Correctness & safety checks SystemVerilog RTL Codegen • Human-readable SystemVerilog • Preserved hierarchy & ECO friendly Libraries Single Source Library • sct_target, sct_initiator, sct_fifo • sct_buffer, sct_pipe, sct_register SystemC Assertion Library • Immediate & temporal assertions • Automatic translation to SVA Common Types & Functions • sct_uint, sct_int (0...∞ width) • Synthesizable utility functions AI & Extension Tools SystemC Skills • Code generation & patterns • Synthesis-aware guidelines Linter Agent • Static analysis & bug detection • Synchronization & fix suggestions VS Code Extension • SystemC Tools extension integration • Pretty printers & syntax support SystemC Compiler Framework Platform • Integrated Hardware Design & Verification Environment

The SystemC Compiler Framework includes the Compiler itself, a number of SystemC libraries for design and testbench code, AI tools, and the SystemC Tools extension for VS Code. Together, these components provide a powerful infrastructure for modern hardware development.

Learning SystemC

Learn SystemC with illustrative examples, training videos, and hundreds of tests included with the Compiler:

LEARN SYSTEMC design • simulate • synthesize IEEE STANDARD 1666-2023 USER GUIDE Compiler workflow TRAINING Slides & videos PUBLICATIONS Papers & methods EXAMPLES Source code </> TEST SUITE Unit tests

SystemC supported

Write hardware design in the SystemC Synthesizable Subset for method and thread processes, and use arbitrary C++ at the elaboration phase, including module constructors. The SystemC Compiler's main features:

  • C++11/14/17/20 support
  • SystemC 3.0.1 included
  • Human-readable SystemVerilog generation
  • CMake-based project, no pragmas or extra scripts
  • Fast translation procedure, typically several minutes
SystemC design top.h dut.h sc_main.cpp CMakeLists.txt Dynamic elaboration Static code analysis with Clang/LLVM Modules and processes code generation SystemVerilog RTL
Initiator → Target handshake between two modules FIFO inter-process buffer & storage Buffer fast FIFO for clocked processes Pipe multi-cycle retiming register Register state for METHOD process Signal / Clock sct_signal, sct_clock, ports Functional interface (TLM 1.0 style) Producer channel Consumer

SingleSource library

Use high-level communication channels and buffers instead of coding handshakes. The SingleSource library provides reliable and efficient implementation of commonly used channels, components, memories and ports. All these components have clear and natural functional interfaces similar to TLM 1.0:

  • Target / Initiator — module-to-module handshake
  • FIFO / Buffer — inter-process buffering & storage
  • Pipe — multi-cycle retiming
  • Register — state for method processes
  • Clock components — for clock and gated clock
  • sct_uint, sct_int — bit-accurate integer types 0...∞ width, mapped to SystemC types
  • Commonly used synthesizable functions

Abstraction level

Run the same SystemC code with SingleSource library components in three modes with equivalent behavior:

  • Cycle-accurate — precise, clock-driven, matches generated SystemVerilog, intended for detailed simulation and synthesis
  • Approximate-timed — data-driven, no clock events, intended for fast functional & performance simulation
  • Loosely-timed — time quantum, faster but less accurate (under construction)
RTL — cycle accurate clock-driven, precise timing • synthesis TLM — approximate timed data-driven events, no clock • fast simulation TLM — loosely timed time quantum • fastest, lower timing accuracy

AI for Everything

Enhance your design architecture and code quality with SystemC Skills and the Linter Agent to:

  • Generate correct and efficient module and process structures
  • Instantiate and connect SystemC and SingleSource channels
  • Write clean, readable, and optimized SystemC code
  • Detect functional and synchronization errors with fix suggestions
SystemC Lint Report Target: ISpanRouter.h 1 Error 2 Warnings Level / Source Finding Fix hint ERROR 270-318 Arbitration fairness and liveness Use per-destination round-robin arbitration WARNING 357-432 Control backpressure and atomic consumption Retain message until put() succeeds WARNING 442-486 Data backpressure and transaction retention Use peek(); get only after acceptance SystemC Linter Agent Actionable fix hints
SystemC Tools — VS Code extension SystemC Tools SystemC Tools includes: • Intel Compiler for SystemC HLS • Common SystemC library • SystemC Skills and Linter Agent • GNU debugger pretty printers • SystemC syntax highlighting SC_MODULE(dut) { sct_target<T> targ; SCT_THREAD(proc, clk); } Linter Agent No issues found SystemC Compiler ready SystemC

VS Code extension

Use SystemC Tools extension in VS Code to enable SystemC coding, debugging and synthesis flow including:

  • Installation and update of the SystemC Compiler
  • AI skills and Linter agent for SystemC
  • SystemC Pretty Printers
  • SystemC syntax highlighting

Getting started

Install the SystemC Compiler from GitHub on most Linux OS and Windows Subsystem for Linux (WSL):

  • Ubuntu, SLES and others
  • Run install.sh for the first installation of the SystemC Compiler and required dependencies
  • Run install_icsc.sh to update and rebuild the SystemC Compiler
  • Use SystemC Tools VS Code extension which does all the installation and update
bash — Linux / WSL $git clone intel/systemc-compiler $./install.sh › building LLVM + SystemC + ICSC ... $*** SystemC Compiler Build and Installation Complete! *** › preparing examples ... $*** Examples are ready to build & run! *** 1. Install install.sh 2. Build svc_target() 3. Get RTL SystemVerilog