SIM_INTERFACE(ppc) {
void (*PYTHON_METHOD clear_atomic_reservation_bit)(conf_object_t *cpu);
void (*PYTHON_METHOD raise_machine_check_exception)(conf_object_t *cpu,
ppc_mc_exc_t exc);
/* Timebase */
unsigned (*PYTHON_METHOD get_timebase_enabled)(conf_object_t *cpu);
void (*PYTHON_METHOD set_timebase_enabled)(conf_object_t *cpu,
unsigned enabled);
/* Power mode */
ppc_sleep_state_t (*PYTHON_METHOD get_sleep_state)(conf_object_t *cpu);
void (*PYTHON_METHOD set_sleep_state)(conf_object_t *cpu,
ppc_sleep_state_t state);
};
#define PPC_INTERFACE "ppc"
The clear_atomic_reservation_bit() function clears the
reservation bit which is set by an lwarx instruction. Clearing the
reservation will cause a following stwcx. instruction to fail.
This function is typically used by a cache hierarchy supporting SMP.
The raise_machine_check_exception() function raises a machine check exception. The exc argument is of the following type:
typedef enum {
Sim_PPC_Generic_MC,
Sim_PPC_MC_TEA,
Sim_PPC_MC_MCP,
Sim_PPC_Bus_Address_Parity,
Sim_PPC_Bus_Data_Parity,
Sim_PPC_Instruction_Cache_Parity,
Sim_PPC_Data_Cache_Parity,
Sim_PPC_L2_Data_Parity,
Sim_PPC_L3_Data_Parity,
Sim_PPC_L3_Address_Parity,
Sim_PPC970_Data_Cache_Parity,
Sim_PPC970_Data_Cache_Tag_Parity,
Sim_PPC970_D_ERAT_Parity,
Sim_PPC970_TLB_Parity,
Sim_PPC970_SLB_Parity,
Sim_PPC970_L2_Load_ECC_Parity,
Sim_PPC970_L2_Page_Table_ECC_Parity,
Sim_PPC970_Uncacheable_Load_Parity,
Sim_PPC970_MC_External
} ppc_mc_exc_t;
The get_timebase_enabled and set_timebase_enabled functions can be used to query and set the enabled state of the timebase.