pcie_port_control port_space
API Reference Manual  /  4 Model-to-Model Interfaces  / 

pmr

Description
SIM_INTERFACE(pmr) {
        uint64 (*get)(
                conf_object_t *obj,
                int pmr_number,
                bool instruction_read);
        void (*set)(
                conf_object_t *obj,
                int pmr_number,
                uint64 value,
                bool instruction_write);
};
#define PMR_INTERFACE "pmr"

This interface provides a way for a user to write their own handler for the performance monitor register bank. The processor's pmr_handler attribute should be set point at the to the module, which implements the pmr interface. When set, all reads and writes toward the defined PMR registers will be forwarded to the user module instead. Simics CPU module will perform all the privilege checks and only forward the read/write if it is permitted.

The supervisor registers are checkpointed by the CPU module and the register content for the PMR registers is distributed to the user module in the finalize phase, after the pmr_handler has been set.

The function get is used for attribute reads, int_register reads or for mfpmr instructions. The value for the PMR register should be returned. The instruction_read will be true only for mfpmr instructions, allowing distinction between register reads by the user and instructions which could have side-effects.

Similar, the set function is used for attribute writes, int_register writes or for mtpmr instructions. The instruction_write will be true only for mtpmr instructions. The value indicates the value written to the PMR register.

Execution Context
Cell Context for all methods.

pcie_port_control port_space