pci_express

Description

Note: This interface is deprecated. The transaction interface implemented by the pcie-bus (upstream and downstream ports) can be used to send any type of message with any type of routing by adding a pcie_info and a pcie_msg_info ATOM to the transaction.

This interface can be implemented by any PCI Express device, switch or endpoint. It is also implemented by the pci-bus, which will pass it on to the other end; e.g. if the endpoint sends a message, the pci-bus will pass it on to the bridge (downport), and if the downport sends it, it will be broadcasted to all devices on the bus.

Please note that message routing is not supported. The implications of this limitation is that a switch does not know if the message is intended for the switch itself or for some device connected to it. In addition, since the bus does not replace the src parameter when forwarding the message, and the bus does not support port mappings, it is impossible for a bus-to-bus bridge (up-port/down-port) to know from which bus the message originates making it impossible to forward the message to the other side.

Another way of looking at this limitation is to say that the only message routing currently supported is the implicit routing that terminates at the receiver (Type[2:0] = 0b100), so bus-to-bus bridges should not try to forward the message to the other side.

src is the object sending the message. type is one of:

typedef enum {
        /* Address Translation */
        PCIE_ATS_Invalidate = 0x01,
        PCIE_PRS_Request    = 0x04,
        PCIE_PRS_Response   = 0x05,

        PCIE_Latency_Tolerance_Reporting = 0x10,
        PCIE_Optimized_Buffer_Flush_Fill = 0x12,

        /* INTx emulation */
        PCIE_Msg_Assert_INTA       = 0x20,
        PCIE_Msg_Assert_INTB       = 0x21,
        PCIE_Msg_Assert_INTC       = 0x22,
        PCIE_Msg_Assert_INTD       = 0x23,
        PCIE_Msg_Deassert_INTA     = 0x24,
        PCIE_Msg_Deassert_INTB     = 0x25,
        PCIE_Msg_Deassert_INTC     = 0x26,
        PCIE_Msg_Deassert_INTD     = 0x27,

        /* Power Management */
        PCIE_PM_Active_State_Nak   = 0x14,
        PCIE_PM_PME                = 0x18,
        PCIE_PM_Turn_Off           = 0x19,
        PCIE_PM_PME_TO_Ack         = 0x1B,

        /* Error Messages */
        PCIE_ERR_COR               = 0x30,
        PCIE_ERR_NONFATAL          = 0x31,
        PCIE_ERR_FATAL             = 0x33,

        /* Locked Transaction */
        PCIE_Unlock                = 0x00,

        /* Slot Power Limit */
        PCIE_Set_Slot_Power_Limit  = 0x50,

        PCIE_Precision_Time_Measurement = 0x52,

        /* Hot Plug Messages */
        PCIE_HP_Power_Indicator_On        = 0x45,
        PCIE_HP_Power_Indicator_Blink     = 0x47,
        PCIE_HP_Power_Indicator_Off       = 0x44,
        PCIE_HP_Attention_Button_Pressed  = 0x48,
        PCIE_HP_Attention_Indicator_On    = 0x41,
        PCIE_HP_Attention_Indicator_Blink = 0x43,
        PCIE_HP_Attention_Indicator_Off   = 0x40,

        PCIE_Vendor_Defined_Type_0 = 0x7e,
        PCIE_Vendor_Defined_Type_1 = 0x7f,

        PCIE_Locked_Transaction    = 0x00,  // legacy name for PCIE_Unlock

        /* Data Link Layer (virtual) Messages

           NOTE: these messages only exist on Simics simulator, as they are
           normally part of the Data Link Layer which is below the level of
           abstraction for Simics PCIe models

           According to PCIe rev 2.0, when a target receives a message that it
           does not recognize or support, except for the "Vendor Defined Type
           1" message, it should treat the request as an "Unsupported Request"
           and report it accordingly (see sec 2.3.1 for reference).
    
           Hence models that comply with rev 2.0 must be updated to either
           1) handle these messages or 2) ignore these messages.

           Ideally we would like to use a new pcie_link interface to transmit
           this information - see bug 17849 for more info. */
        PCIE_DLL_Link_Down = -1,
        PCIE_DLL_Link_Up = -2,
} pcie_message_type_t;

The contents of payload depends on type.

SIM_INTERFACE(pci_express) {
        int (*send_message)(conf_object_t *dst, conf_object_t *src,
                            pcie_message_type_t type, byte_string_t payload);
};
#define PCI_EXPRESS_INTERFACE "pci_express"

Execution Context

Cell Context for all methods.