Core_DSTC_Flush_Counter Core_Exception_Return
API Reference Manual  /  12 Haps  / 

Core_Exception

Description
Triggered when an exception/trap is taken by a processor. The hap occurs before side-effects, control transfers included, have taken place.

Interrupting the simulation by calling SIM_break_simulation inside the hap will cause the simulation to stop right before the exception (and the trapping instruction, if any). The simulation state will then be as it was prior to the execution of the instruction or exception. Continuing the simulation will then re-run the exception, this time without calling hap functions.

Depending on the processor model, some state may actually have changed in an idempotent way when the hap occurs, but this should not be relied upon.

The exact meaning of the exception number depends on the simulated processor architecture. The exception interface can be used to translate the number to an exception name.

Callback Type
void (*)(lang_void *callback_data, 
         conf_object_t *trigger_obj, 
         int64 exception_number);

Index
exception_number

Core_DSTC_Flush_Counter Core_Exception_Return