The standard limitations may apply to all model products.
- Error states and diagnostic registers typically only return default values
corresponding to no error when read.
- Performance counters will only return approximate values.
- Hardware models are simplified for performance and complexity reasons, as
long as target software in the Delivery Criteria can run unmodified on the
model.
- Only listed components or models will be implemented. Listed components or
models can have limited functionality as long as the Delivery Criteria are
fulfilled.
- The default in-order execution model in Simics allows one instruction or
exception to be simulated each simulated clock tick. This means that the
simulated processors implicitly have a “firm” consistency model. Unless
otherwise specified, the in-order execution model is the only execution
model supported.
- Simics is timing approximate; while Simics maintains a conceptual model of
execution time, it will vary from the execution time of the same software
running on a particular instance of physical hardware.
- Processor and device models simulate the architecturally defined behavior,
usually defined in a Programmers Reference Manual. The Simics implementation
of processor and device models may differ from hardware implementations but
will comply with the architecture unless otherwise specified.
- For unusual cases, floating point calculations may have rounding errors,
causing low order bits to differ from what is defined by architecture.
- While error status registers are available in the simulation model, they
typically have read-write semantics without any side effects. This means
they are not set by the simulation model and setting the registers will not
cause any other effects in the model (such as triggering an interrupt or
setting other registers).
- Deviations from product specification will be noted in the release notes.