SIM_STC_flush_cache, SIM_flush_I_STC_logical, SIM_flush_D_STC_logical, SIM_flush_I_STC_physical, SIM_flush_D_STC_physical — flush or remove entries in the STCs of a cpu
#include <simics/processor-api.h> // in C
import "simics/processor-api.dml"; // in DML
void
SIM_STC_flush_cache(conf_object_t *NOTNULL cpu);
void
SIM_flush_I_STC_logical(conf_object_t *NOTNULL cpu,
logical_address_t vaddr,
logical_address_t length);
void
SIM_flush_D_STC_logical(conf_object_t *NOTNULL cpu,
logical_address_t vaddr,
logical_address_t length);
void
SIM_flush_I_STC_physical(conf_object_t *NOTNULL cpu,
physical_address_t paddr,
physical_address_t length);
void
SIM_flush_D_STC_physical(conf_object_t *NOTNULL cpu,
physical_address_t paddr,
physical_address_t length,
read_or_write_t read_or_write);
import simics
simics.SIM_STC_flush_cache(...)
simics.SIM_flush_I_STC_logical(...)
simics.SIM_flush_D_STC_logical(...)
simics.SIM_flush_I_STC_physical(...)
simics.SIM_flush_D_STC_physical(...)
These functions remove entries from the Simics internal caches (STCs) or completely flushes the STCs contents. Memory mappings which have been cached in the STCs will be faster for Simics to execute. Simics extensions such as a cache model will need to flush entries in the STC when a cache line is replaced, in order to be called when a cache line is used again.
SIM_STC_flush_cache flushes the entire contents of the STCs (both instruction and data) from the specified cpu.
The SIM_flush_xxx functions removes specified memory ranges in the instruction or data STC. The address range is either the logical or the physical address. The read_or_write parameter specifies whether the read or the write D-STC should be flushed. If the function doesn’t have such a parameter, both read and write D-STCs are flushed. The flushed address range is at least [ vaddr … (vaddr + length - 1) ], but may be larger. SIM_flush_D_STC_logical currently always flushes an entire page.
The SIM_flush_xxx functions can only be used on CPUs that implement the internal stc interface; hence, they can not be used on user-defined CPU models.
Cell Context
SIM_flush_all_caches — clear Simics’s internal caches
#include <simics/simulator-api.h> // in C
import "simics/simulator-api.dml"; // in DML
void
SIM_flush_all_caches();
import simics
simics.SIM_flush_all_caches(...)
Clears Simics’s internal caches such as STC contents and intermediate code. This function is mainly for internal use (for debugging purposes) and may be removed in the future.
Global Context
SIM_flush_cell_caches — clear internal caches for a given cell
#include <simics/simulator-api.h> // in C
import "simics/simulator-api.dml"; // in DML
void
SIM_flush_cell_caches(conf_object_t *NOTNULL obj);
import simics
simics.SIM_flush_cell_caches(...)
Clears internal caches in Simics for a given cell, such as STC contents and intermediate code.
Cell Context