riscv_instruction_action interface helps with
implementing semantics for user defined instruction.
The cpu argument in all methods below is the processor object implementing this interface.
X registers
read_X_register return the current value of X register number.
write_X_register updates the value of X register number to
value.
To help with disassembly name_X_register returns the name of the X
register number.
Control and status registers, CSRs
These accesses are not seen as instruction accesses, all access checks are
bypassed and no exception will be thrown.
read_CSR returns current value of the CSR at address.
write_CSR updates the value of the CSR at address to
value. Not all bits of all CSRs is writable.
Memory accesses using logical address
A logical address is passed through MMU based on current mode. This means that
an access can raise exception for page fault or illegal access.
read_memory returns a value of size> bytes zero extended to
64 bits from memory at address/
write_memory writes size bytes to memory at address.
Both read_memory and write_memory can raise exception for unaligned data access if
the core does not support unaligned accesses.
load_memory_buf loads buf.len bytes from address
to buf.
store_memory_buf writes buf.len bytes from buf to
address.
These methods do not raise exception for unaligned accesses, instead large and/or
unaligned accesses are broken down to multiple smaller aligned accesses.
Other get_current_cpu_mode returns current cpu mode. raise_exception raises exception with code put in th xCAUSE CSR and tval put in the xTVAL CSR.
SIM_INTERFACE(riscv_instruction_action) {
uint64 (*read_x_register)(conf_object_t *cpu, uint32 number);
void (*write_x_register)(conf_object_t *cpu, uint32 number, uint64 value);
const char * (*name_x_register)(conf_object_t *cpu, uint32 number);
uint64 (*read_csr)(conf_object_t *cpu, uint32 address);
void (*write_csr)(conf_object_t *cpu, uint32 address, uint64 value);
// Logical address
uint64 (*read_memory)(conf_object_t *cpu, uint64 address,
uint32 size);
void (*write_memory)(conf_object_t *cpu, uint64 address,
uint32 size, uint64 value);
void (*load_memory_buf)(conf_object_t *cpu, uint64 address, buffer_t buf);
void (*store_memory_buf)(conf_object_t *cpu, uint64 address, bytes_t buf);
riscv_cpu_mode_t (*get_current_cpu_mode)(conf_object_t *cpu);
void (*raise_exception)(conf_object_t *cpu, uint64 code, uint64 tval);
};
#define RISCV_INSTRUCTION_ACTION_INTERFACE "riscv_instruction_action"