riscv_coprocessor

Description

The riscv_coprocessor interface makes it possible for RISC-V processors to read and write Control and Status Registers (CSRs) like mtime

SIM_INTERFACE(riscv_coprocessor) {
        uint64 (*read_register)(conf_object_t *obj, uint64 number);
        void (*write_register)(conf_object_t *obj, uint64 number, uint64 value);
};

#define RISCV_COPROCESSOR_INTERFACE "riscv_coprocessor"

Execution Context

Cell Context for all methods.