8.12 Using a cache model

Let us now show a simple example of how to use simple cache model. By default, the Intel Simics simulator does not model any cache system. It uses its own memory system to achieve high speed simulation and modelling a hardware cache model would only slow it down. However, via the instrumentation framework, the flow of memory operations coming from the processor can be captured, and this allows modelling caches.

Here is an example of using instrumentation to connect a simple cache model.

• Start the with the qsp-x86/firststeps target.

  $ ./simics qsp-x86/firststeps
  

• Create the cache tool and connect it to all processors.

  simics> new-simple-cache-tool name = cachetool -connect-all
  [board.mb.cpu0.core[0][0] info] VMP not engaged. Reason: instrumentation enabled.
  Created cachetool (connected to 1 provider)
  

• Create caches on the processors.

  simics> (cachetool.add-l1d-cache name = l1d line-size = 64 sets = 64 ways = 12 -ip-read-prefetcher prefetch-additional = 1)
  Created cache board.mb.cpu0.cache[0].l1d
  simics> (cachetool.add-l1i-cache name = l1i line-size = 64 sets = 64 ways = 8)
  Created cache board.mb.cpu0.cache[0].l1i
  simics> (cachetool.add-l2-cache name = l2 line-size = 64 sets = 1024 ways = 20 -prefetch-adjacent prefetch-additional = 4)
  Created cache board.mb.cpu0.cache[0].l2
  simics> (cachetool.add-l3-cache name = l3 line-size = 64 sets = 8192 ways = 12)
  Created cache board.mb.cpu0.l3
  

• Run the simulation.

  simics> run 55 s
  

• Display one of the cache statistics.

  simics> board.mb.cpu0.cache[0].l1d.print-statistics
  ┌─────┬───────────────────────────────────┬──────────┬─────┐
  │Row #│              Counter              │  Value   │  %  │
  ├─────┼───────────────────────────────────┼──────────┼─────┤
  │    1│read accesses                      │3008859511│     │
  │    2│read misses                        │  36862357│ 1.23│
  │    3│write accesses                     │1459380293│     │
  │    4│write misses                       │  16132103│ 1.11│
  │    5│prefetch accesses                  │  66601575│     │
  │    6│prefetch misses                    │  40928644│61.45│
  │    7│prefetched lines used              │  17449124│26.20│
  │    8│prefetch instructions              │   6317961│     │
  │    9│evicted lines (total)              │  93922336│     │
  │   10│evicted modified lines             │  31215791│33.24│
  │   11│entire cache flushes (invd, wbinvd)│        12│     │
  │   12│uncachable read accesses           │ 112466598│     │
  │   13│uncachable write accesses          │  73099098│     │
  └─────┴───────────────────────────────────┴──────────┴─────┘
  

Source code for cache model is in the base package under: src/extensions/simple-cache-tool.