SystemVerilogSynthesizerConfiguration class
Configuration for SystemVerilog synthesis.
Constructors
- SystemVerilogSynthesizerConfiguration({SystemVerilogPortTypeConfiguration inputPortType = const SystemVerilogPortTypeConfiguration(objectType: SystemVerilogPortType.implicit), SystemVerilogPortTypeConfiguration outputPortType = const SystemVerilogPortTypeConfiguration(objectType: SystemVerilogPortType.implicit), SystemVerilogPortTypeConfiguration inOutPortType = const SystemVerilogPortTypeConfiguration(dataType: SystemVerilogPortType.implicit)})
-
Creates a new configuration for SystemVerilog synthesis.
const
Properties
- hashCode → int
-
The hash code for this object.
no setterinherited
- inOutPortType → SystemVerilogPortTypeConfiguration
-
Type configuration for inout ports.
final
- inputPortType → SystemVerilogPortTypeConfiguration
-
Type configuration for input ports.
final
- outputPortType → SystemVerilogPortTypeConfiguration
-
Type configuration for output ports.
final
- runtimeType → Type
-
A representation of the runtime type of the object.
no setterinherited
Methods
-
noSuchMethod(
Invocation invocation) → dynamic -
Invoked when a nonexistent method or property is accessed.
inherited
-
toString(
) → String -
A string representation of this object.
inherited
Operators
-
operator ==(
Object other) → bool -
The equality operator.
inherited