instantiationVerilog method
Generates custom SystemVerilog to be injected in place of a module
instantiation.
The instanceType
and instanceName
represent the type and name,
respectively of the module that would have been instantiated had it not
been overridden. ports
is a mapping from the Module's port names to
the names of the signals that are passed into those ports in the generated
SystemVerilog.
If a standard instantiation is desired, either return null
or use
SystemVerilogSynthesizer.instantiationVerilogFor with
forceStandardInstantiation
set to true
. By default, null
is
returned and thus a standard instantiation is used.
Implementation
String? instantiationVerilog(
String instanceType,
String instanceName,
Map<String, String> ports,
) =>
null;