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rohd
rohd
SimpleClockGenerator
clk property
clk
brightness_4
clk
property
Null safety
Logic
clk
The generated clock.
Implementation
Logic get clk => output('clk');
rohd
rohd
SimpleClockGenerator
clk property
SimpleClockGenerator class
Constructors
SimpleClockGenerator
Properties
clk
clockPeriod
combinationalPaths
definitionName
hasBuilt
hashCode
inputs
internalSignals
name
outputs
parent
reserveDefinitionName
reserveName
reverseCombinationalPaths
runtimeType
signals
subModules
uniqueInstanceName
Methods
addInput
addOutput
build
generateSynth
getCombinationalPaths
hierarchy
hierarchyString
input
instantiationVerilog
isInput
isOutput
isPort
noSuchMethod
output
toString
Operators
operator ==