ReplicationOp constructor
Constructs a ReplicationOp
The signal original
will be repeated over the _multiplier
times as an
output.
Input _multiplier
cannot be negative or zero, an exception will be
thrown, otherwise.
Module is in-lined as SystemVerilog, it will use {width{bit}}
Implementation
ReplicationOp(Logic original, this._multiplier)
: _inputName = Naming.unpreferredName(original.name),
_outputName = Naming.unpreferredName('replicated_${original.name}') {
final newWidth = original.width * _multiplier;
if (newWidth < 1) {
throw InvalidMultiplierException(newWidth);
}
addInput(_inputName, original, width: original.width);
addOutput(_outputName, width: original.width * _multiplier);
_setup();
}