ReplicationOp constructor

ReplicationOp(
  1. Logic original,
  2. int _multiplier
)

Constructs a ReplicationOp

The signal original will be repeated over the _multiplier times as an output. Input _multiplier cannot be negative or zero, an exception will be thrown, otherwise. Module is in-lined as SystemVerilog, it will use {width{bit}}

Implementation

ReplicationOp(Logic original, this._multiplier)
    : _inputName = Naming.unpreferredName(original.name),
      _outputName = Naming.unpreferredName('replicated_${original.name}'),
      _isNet = original.isNet {
  final newWidth = original.width * _multiplier;
  if (newWidth < 1) {
    throw InvalidMultiplierException(newWidth);
  }

  if (_isNet) {
    original = addInOut(_inputName, original, width: original.width);

    replicated =
        LogicNet(name: _outputName, width: newWidth, naming: Naming.unnamed);
    final internalOut = addInOut(_outputName, replicated, width: newWidth);

    for (var i = 0; i < _multiplier; i++) {
      internalOut.quietlyMergeSubsetTo(original as LogicNet,
          start: i * original.width);
    }
  } else {
    addInput(_inputName, original, width: original.width);
    replicated = addOutput(_outputName, width: original.width * _multiplier)
      ..makeUnassignable(
          reason: 'Output of a gate $this cannot be assigned.');
    _setup();
  }
}