acceptsEmptyPortConnections property

  1. @override
bool get acceptsEmptyPortConnections
override

Indicates whether this module accepts empty port connections when being instantiated in SystemVerilog.

This may be safely set to true in cases where the instantiation verilog can accept port connections like .port_name() where no signal is connected to that port.

Implementation

@override
bool get acceptsEmptyPortConnections => false;