generateSynth method

String generateSynth({
  1. SystemVerilogSynthesizerConfiguration configuration = const SystemVerilogSynthesizerConfiguration(),
})
inherited

Returns a synthesized version of this Module.

Currently returns one long file in SystemVerilog, but in the future may have other output formats, languages, files, etc.

The configuration controls options specific to SystemVerilog output.

Implementation

String generateSynth({
  SystemVerilogSynthesizerConfiguration configuration =
      const SystemVerilogSynthesizerConfiguration(),
}) {
  if (!_hasBuilt) {
    throw ModuleNotBuiltException(this);
  }

  final synthHeader = '''
/**
 * Generated by ROHD - www.github.com/intel/rohd
 * Generation time: ${Timestamper.stamp()}
 * ROHD Version: ${Config.version}
 */

''';
  return synthHeader +
      SynthBuilder(
        this,
        SystemVerilogSynthesizer(configuration: configuration),
      ).getSynthFileContents().join('\n\n////////////////////\n\n');
}