Memory constructor
- Logic clk,
- Logic reset,
- List<
DataPortInterface> writePorts, - List<
DataPortInterface> readPorts, { - String name = 'memory',
Construct a new memory.
Must provide at least one port (read or write).
Implementation
Memory(Logic clk, Logic reset, List<DataPortInterface> writePorts,
List<DataPortInterface> readPorts,
{super.name = 'memory'})
: numWrites = writePorts.length,
numReads = readPorts.length,
dataWidth = (writePorts.isNotEmpty)
? writePorts[0].dataWidth
: (readPorts.isNotEmpty)
? readPorts[0].dataWidth
: 0, // at least one of these must exist
addrWidth = (writePorts.isNotEmpty)
? writePorts[0].addrWidth
: (readPorts.isNotEmpty)
? readPorts[0].addrWidth
: 0 // at least one of these must exist
{
if (writePorts.isEmpty && readPorts.isEmpty) {
throw RohdHclException(
'Must specify at least one read port or one write port.');
}
if (readLatency < 0) {
throw RohdHclException('Read latency must be non-negative.');
}
// make sure widths of everything match expectations
for (final port in [...writePorts, ...readPorts]) {
if (port.addrWidth != addrWidth) {
throw RohdHclException('All ports must have the same address width.');
}
if (port.dataWidth != dataWidth) {
throw RohdHclException('All ports must have the same data width.');
}
}
addInput('clk', clk);
addInput('reset', reset);
for (var i = 0; i < numReads; i++) {
rdPorts.add(readPorts[i].clone()
..connectIO(this, readPorts[i],
inputTags: {DataPortGroup.control},
outputTags: {DataPortGroup.data},
uniquify: (original) => 'rd_${original}_$i'));
}
for (var i = 0; i < numWrites; i++) {
wrPorts.add(writePorts[i].clone()
..connectIO(this, writePorts[i],
inputTags: {DataPortGroup.control, DataPortGroup.data},
outputTags: {},
uniquify: (original) => 'wr_${original}_$i'));
}
}