FloatingPointAdderRound class - rohd_hcl library

Constructors

FloatingPointAdderRound(FloatingPoint a, FloatingPoint b, {Logic? subtract, Logic? clk, Logic? reset, Logic? enable, Adder adderGen(Logic, Logic) = ParallelPrefixAdder.new, ParallelPrefix ppTree(List<Logic>, Logic (Logic, Logic)) = KoggeStone.new, String name = 'floating_point_adder_round'}): Add two floating point numbers a and b, returning result in sum. subtract is an optional Logic input to do subtraction adderGen is an adder generator to be used in the primary adder functions. ppTree is an ParallelPrefix generator for use in increment /decrement functions.

Properties

clk ↔ Logic?: The clk: if a valid clock signal is passed in, a pipestage is added to the adder to help optimize frequency.
getter/setter pair
definitionName → String: The definition name of this Module used when instantiating instances in generated code.
no setterinherited
enable ↔ Logic?: Optional enable, used only if a clk is not null to enable the pipeline flops.
getter/setter pair
exponentWidth → int: Must be greater than 0.
final
hasBuilt → bool: Indicates whether this Module has had the build method called on it.
no setterinherited
hashCode → int: The hash code for this object.
no setterinherited
inputs → Map<String, Logic>: A map from input port names to this Module to corresponding Logic signals.
no setterinherited
internalSignals → Iterable<Logic>: An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
no setterinherited
mantissaWidth → int: Must be greater than 0.
final
name → String: The name of this Module.
finalinherited
outputs → Map<String, Logic>: A map from output port names to this Module to corresponding Logic signals.
no setterinherited
parent → Module?: The parent Module of this Module.
no setterinherited
reserveDefinitionName → bool: If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
finalinherited
reserveName → bool: If true, guarantees uniqueInstanceName matches name or else the build will fail.
finalinherited
reset ↔ Logic?: Optional reset, used only if a clk is not null to reset the pipeline flops.
getter/setter pair
runtimeType → Type: A representation of the runtime type of the object.
no setterinherited
signals → Iterable<Logic>: An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
no setterinherited
subModules → Iterable<Module>: An Iterable of all Modules contained within this Module.
no setterinherited
sum → FloatingPoint: Output FloatingPoint representing the sum of two input FloatingPoints
latefinal
uniqueInstanceName → String: If this module has a parent, after build this will be a guaranteed unique name within its scope.
no setterinherited

Methods

addInput(String name, Logic x, {int width = 1}) → Logic: Registers a signal as an input to this Module and returns an input port that can be consumed.
inherited
addInputArray(String name, Logic x, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Registers and returns an input LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addOutput(String name, {int width = 1}) → Logic: Registers an output to this Module and returns an output port that can be driven.
inherited
addOutputArray(String name, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Registers and returns an output LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
build() → Future<void>: Builds the Module and all subModules within it.
inherited
generateSynth() → String: Returns a synthesized version of this Module.
inherited
hierarchy() → Iterable<Module>: Returns an Iterable of Modules representing the hierarchical path to this Module.
inherited
hierarchyString([int indent = 0]) → String: Returns a pretty-print String of the heirarchy of all Modules within this Module.
inherited
input(String name) → Logic: Accesses the Logic associated with this Modules input port named name.
inherited
isInput(Logic net) → bool: Returns true iff net is the same Logic as the input port of this Module with the same name.
inherited
isOutput(Logic net) → bool: Returns true iff net is the same Logic as the output port of this Module with the same name.
inherited
isPort(Logic net) → bool: Returns true iff net is the same Logic as an input or output port of this Module with the same name.
inherited
noSuchMethod(Invocation invocation) → dynamic: Invoked when a nonexistent method or property is accessed.
inherited
output(String name) → Logic: Accesses the Logic associated with this Modules output port named name.
inherited
toString() → String: A string representation of this object.
inherited
tryInput(String name) → Logic?: Provides the input named name if it exists, otherwise null.
inherited
tryOutput(String name) → Logic?: Provides the output named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool: The equality operator.
inherited